makefile: all current .c files compile directory as a separate executable object file

        Sometimes this is the case, for example, in the learning process of the study, a catalog written a lot of c language source files, each of which is a separate executable. Each possibility is a separate sample.

       This is when you need a makefile, each file separately can be compiled into an executable file, not every document will have to write a gcc -c xxx.c -o xxx.

       Here is a simple wording: xxx.c all files in the current directory can be compiled into a single file xxx.

PHONY: all  clean
SRC=$(wildcard *.c)
OBJ=$(SRC:%.c=%.o)
BIN=$(OBJ:%.o=%)

CC=gcc
CFLAGS=-Wall -g -c

all:$(BIN)

$(BIN):%:%.o
        $(CC) $^ -o $@
$(OBJ):%.o:%.c
        $(CC) $(CFLAGS) $^ -o $@

clean:
        rm $(OBJ) $(BIN)

If you use the automatic derivation, it can be more simple:

.PHONY: all  clean
SRC=$(wildcard *.c)
BIN=$(SRC:%.c=%)

CC=gcc
#CFLAGS=-Wall -g -c

all:$(BIN)

clean:
        rm  $(BIN)