STM32CubeMx hardware IIC driver EEPROM

1. Introduction to I2C

The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, which is used to connect microcontrollers and their peripheral devices. It is a bus standard widely used in the field of microelectronic communication control. It has the advantages of less interface lines, simple control method, small device package and high communication rate.
I2C characteristics:
(1) Only two bus lines are required, one serial data line SDA, and one serial clock line SCL;
(2) Each device connected to the bus can pass a unique address and a simple host/ The slave relationship software sets the address, the master can act as a master transmitter or a master receiver;
(3) It is a true multi-master bus, if two or more masters initiate data transfer at the same time, data can be prevented by collision detection and arbitration (4) Serial 8-bit bidirectional data transfer bit rate up to 100kbit/s in standard mode, 400kbit
/s in fast mode, and 3.4Mbit/s in high-speed mode
(5) On-chip filtering The device can filter out the glitches on the bus data line to ensure the integrity of the data;
(6) The number of ICs connected to the same bus is only limited by the maximum capacitance of the bus, 400pF;
IIC is a serial communication bus, synchronous transmission, half-duplex

2. I2C bus protocol

IIC protocol format: start signal, stop signal, response signal, non-response signal, send data, receive data.
Idle state: both SCL and SDA remain high;

2.1 Start signal

When the clock is high, the data changes from high to low.

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SDA_OUT=1;
SCL=1;
delay_us(2);
SDA_OUT=0;
//方便下一次数据收发
delay_us(2);
SCL=0;

2.2 Stop Signal

When the clock line is high, the data line changes from low to high.

SDA_OUT=0;
SCL=0;
Delay_us(2);
SCL=1;
Delay_us(2);
SDA_OUT=1;

Data transmission timing:
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2.3 Get response

Data is read while the clock line is high. The reply signal itself is a bit of data.

u8 i=0;
SCL=0;//告诉从机，主机需要读取数据
Delay_us(2);
SCL=1;//开始读取数据
while(SDA_IN)
{
    
    
  i++;
  Delay_us(1);
  if(i>=20)return 1;//非应答
}
Delay_us(2);
SCL=0;//方便下一次数据收发
return 0;//获取应答信号

2.4 Sending acknowledgment (non-acknowledgment) signals

Data is sent when the clock line is low. The reply signal itself is a bit of data.

SCL=0;
SDA_OUT=ack&0x01;//ack为应答参数，0为应答，1为非应答
Delay_us(2);
SCL=1;//数据发送完成
//方便下一次数据收发
Delay_us(2);
SCL=0;

2.5 Send one byte of data

for(i=0;i<8;i++)
{
    
    
  SCL=0;
  if(data&0x80)SDA_OUT=1;
  else SDA_OUT=0；
  Delay_us(2);
SCL=1;//数据发送完成
data<<=1;
Delay_us(2);
}
SCL=0;//方便下一次数据收发

2.6 Receive a byte of data

u8 data=0; 
for(i=0;i<8;i++)
{
    
    
SCL=0;//告诉从机，主机需要读取数据
Delay_us(2);
SCL=1;//主机开始读取数据
data<<=1;
if(SDA_IN)data|=0x01;
Delay_us(2);
}
SCL=0;//方便下一次数据收发
return data;

3. Introduction of AT24CXX

CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K bit serial CMOS E2PROM. Internally contains 12/256/512/1024/2048 8-bit bytes, CATALYST's advanced CMOS technology substantially reduces the power consumption of the device, CAT24WC01 has an 8-byte page write buffer, CAT24WC02/04/08/16 There is a 16-byte page write buffer, and the device operates through the I2C bus interface with a dedicated write protection feature.
Features  Compatible with 400KHz
I2C bus  1.8 to
6.0V operating voltage range 
Low power CMOS technology Erase cycle  Data retention for 100 years  8-pin DIP SOIC or TSSOP package  Temperature range: commercial grade, industrial grade and automotive grade

3.1 Pin Description

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3.2 Bus Timing

Data is read on the rising edge of the clock, and data is sent on the falling edge.
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3.3 Slave Address

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3.4 Write operation timing

Byte write
In byte write mode, the master device sends the start command and slave device address information (R/W bit is zero) to the slave device. After the slave device generates a response signal, the master device sends CAT24WC01/02/04/08/ 16 byte address, the master device sends data to the addressed storage unit after receiving another response signal from the slave device. AT24WC01/02/04/08/16 responds again, and starts to erase and write internal data after the master device generates a stop signal. During the internal erasing and rewriting process, CAT24WC01/02/04/08/16 no longer responds to any ask.
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Page write
uses page write, CAT24WC01 can write 8 bytes of data at a time, CAT24WC02/04/08/16 can write 16 bytes of data at a time. The start of a page write operation is the same as that of a byte write, except that a stop signal is not generated after a byte of data is transferred. The master device is allowed to send P (AT24WC01 P=7; AT24WC02/04/08/16 P=15) additional bytes, and the CAT24WC01/02/04/08/16 generates an acknowledge bit after each byte of data is sent And add 1 to the low bit of the byte address, and keep the high bit unchanged.
If the master sends more than P+1 bytes before sending the stop signal, the address counter will automatically roll over and the previously written data will be overwritten.
After receiving the P+1 byte data and the stop signal sent by the master device, CAT24CXXX starts the internal write cycle to write the data to the data area. All received data is written to CAT24WC01/02/04/08/16 within one write cycle.
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3.5 Read Operation Timing

Selective Read
Selective read allows the master to read any byte of the register. The master first performs a pseudo-write operation by sending a start signal, the slave address, and the address of the byte of data it wants to read. After the CAT24WC01/02/04/08/16 responds, the master re-sends the start signal and the slave address, at this time the R/W bit is set to 1, CAT24WC01/02/04/08/16 responds and sends the acknowledge signal, and then outputs Requested for an 8-bit byte of data, the master does not send an acknowledge signal but generates a stop signal.
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Sequential Read
Sequential read operations can be initiated with immediate read or selective read operations. After CAT24WC01/02/04/08/16 sends an 8-bit byte data, the master device generates a response signal to respond, telling CAT24WC01/02/04/08/16 that the master device requires more data, corresponding to each The response signal CAT24WC01/02/04/08/16 generated by the host will send an 8-bit data byte. This operation ends when the master sends a stop bit instead of an acknowledge.
The data output from CAT24WC01/02/04/08/16 is output from N to N+1 in order. During read operation, the address counter is incremented in the entire address of CAT24WC01/02/04/08/16, so that the entire register area can be read out in one read operation. When the bytes read exceeds E (for 24WC01, E=127; for 24WC02, E=255; for 24WC04, E=511; for 24WC08, E=1023; for 24WC16 E=2047) the counter rolls over to zero and continues Output data bytes.
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4. EEPROM hardware interface

The EEPROM chip used in this example is AT24C08, which is fully compatible with 24C02;
the capacity of AT24C08 is 8Kbit, that is, 1KB, and 1024 bytes; the capacity of 24C02 is 2kbit, which is 256 bytes.

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pin	GPIO
IIC_SCL	Clock line PB6
IIC_SDA	Bidirectional data line PB7

5. Software settings

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6. Code Generation

6.1 IIC hardware configuration

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6.2 IIC hardware generates start signal and stop signal

//产生起始信号
void IIC_Start(void)
{
    
    
   hi2c1.Instance->CR1|=1<<8;
   while(!(hi2c1.Instance->SR1&1<<0)){
    
    }//等待起始信号发送成功
   hi2c1.Instance->CR1&=~(1<<8);
}
//停止信号
void IIC_Stop(void)
{
    
    
	hi2c1.Instance->CR1|=1<<9;
}

6.3 IIC hardware data transceiver

//发送数据
void IIC_WriteData(uint8_t data)
{
    
    
   hi2c1.Instance->DR=data;
   while(!(hi2c1.Instance->SR1&1<<7)){
    
    }//等待数据发送完成
   
}
/*发送地址*/
void IIC_WriteAddr(uint8_t adrr)
{
    
    
	uint8_t stat;
	hi2c1.Instance->DR=adrr;
	while(!(hi2c1.Instance->SR1&1<<1)){
    
    }//等待数据发送完成
	stat=hi2c1.Instance->SR2;//对SR2读取清除标志位
}
uint8_t IIC_readData(void)
{
    
    
	uint8_t data;
	hi2c1.Instance->CR1|=1<<10;//产生应答
	while(!(hi2c1.Instance->SR1&1<<6)){
    
    }//等待数据到来
	data=hi2c1.Instance->DR;
	hi2c1.Instance->CR1&=~(1<<10);//取消应答发送
	return data;
}

6.4 AT24C08 read and write bytes

#define AT24C08_ADDR_W 0xA0  //器件地址+写使能位
#define AT24C08_ADDR_R 0xA1  //器件地址+读使能位
/*写一个字节函数*/
void AT24C08_WriteOneByte(uint8_t addr,uint8_t data)
{
    
    
	IIC_Start();//发送起始信号
	IIC_WriteAddr(AT24C08_ADDR_W);//发送地址
	IIC_WriteData(addr);//发送写入数据地址
	IIC_WriteData(data);//写入数据
	IIC_Stop();//停止信号
	HAL_Delay(10);//写周期时间
}
/*读一个字节函数*/
uint8_t AT24C08_ReadOneByte(uint8_t addr)
{
    
    
	uint8_t data;  
	IIC_Start();//发送起始信号
	IIC_WriteAddr(AT24C08_ADDR_W);//器件地址+写使能
	IIC_WriteData(addr);//发送写入数据地址
	IIC_Start();//发送起始信号
	IIC_WriteAddr(AT24C08_ADDR_R);//器件地址+读使能
	data=IIC_readData();//读取一个字节数据
	IIC_Stop();//停止信号
	return data;
}

6.5 Main function

  MX_GPIO_Init();
  MX_USART1_UART_Init();
  //MX_FSMC_Init();
  MX_SPI2_Init();
  MX_I2C1_Init();
  /* USER CODE BEGIN 2 */
   printf("串口初始化完成\n");
	uint8_t buff_tx[]="STM32CubeMX硬件IIC驱动AT24C08数据读写测试! --VER1.0";
   uint8_t buff_rx[100];
   uint8_t data;
//NT35310_Init();//LCD初始化
   AT24C08_WriteData(100,buff_tx,sizeof(buff_tx));
   AT24C08_ReadData(100,buff_rx,sizeof(buff_tx));
   printf("buff_rx=%s\r\n",buff_rx);
  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    
    
    /* USER CODE END WHILE */
    /* USER CODE BEGIN 3 */
  }

Note: STM32F10x hardware IIC and FSMC cannot be used at the same time;
It is stated in the STM32 errata manual:
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6.6 Example effect

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