Difference between mips delay slot bnez and bnezl

Since the instructions of mips take the form of pipeline. Instruction fetch decode to perform memory operation write-back

So in the case of jumps and branches. When a branch is executed, the next instruction has already been executed.

80031DB8  bnez    $v0, loc_80031F58
80031DBC  move    $v0, $zero

For example the above command.

BNEZ是branch not equal to zero

When BNEZ enters the execution stage and has not been executed, move enters the decoding stage that has not been executed

When BNEZ is executed (the V0 at this time is the previous V0). After the move decoding is completed, it must be able to execute next.

So it doesn't matter whether BNEZ jumps or not. V0 will be modified to 0

This is bnez.

And BNEZL is a big article on the possibility of branch not equal to zero likely. Likely indicates a high probability. unlikely means low probability.

Not so for BNEZL.

80031DB8  bnezl    $v0, loc_80031F58
80031DBC  move    $v0, $zero

bnezl indicates that the jump must be established. The next delay slot will be executed.

If v0 was not 0 before. Then it will jump to 1F58 here. At this point, the jump is established. Then move v0,0 will be executed.

If v0 is 0, then no jump to 1F58. The jump does not hold. Then move v0,0 will not be executed.

If you set a breakpoint in the branch likely delay slot. Then it will only break when the conditions are met.

see explanation

https://www.math.ku.edu/computing/cluster/totalview.6.0.0-0-doc/ref_guide/architectures29.html

MIPS Delay Slot Instructions On the MIPS architecture, jump and branch instructions have a "delay slot". This means that the instruction after the jump or branch instruction is executed before the jump or branch is executed. In addition, there is a group of "branch likely" conditional branch instructions in which the instruction in the delay slot is executed only if the branch is taken. The MIPS processors execute the jump or branch instruction and the delay slot instruction as an indivisible unit. If an exception occurs as a result of executing the delay slot instruction, the branch or jump instruction is not executed, and the exception appears to have been caused by the jump or branch instruction. This behavior of the MIPS processors affects both the TotalView instruction step command and TotalView breakpoints. The TotalView instruction step command will step both the jump or branch instruction and the delay slot instruction as if they were a single instruction. If a breakpoint is placed on a delay slot instruction, execution will stop at the jump or branch preceding the delay slot instruction, and TotalView will not know that it is at a breakpoint. At this point, attempting to continue the thread that hit the breakpoint without first removing the breakpoint will cause the thread to hit the breakpoint again without executing any instructions. Before continuing the thread, you must remove the breakpoint. If you need to reestablish the breakpoint, you might then use the instruction step command to execute just the delay slot instruction and the branch. A breakpoint placed on a delay slot instruction of a branch likely instruction will be hit only if the branch is going to be taken.