Enhanced anti-interference is one of the reasons
Standard UART can choose 16 times sampling, or 64 times sampling, I think it should be convenient for frequency division design.
The RXD front end of the standard UART has a "1 to 0 transition detector". When it receives the ground level on 8 RXDs continuously, the detector considers that the RXD line has a start bit and enters the state of receiving data. Accept the state, accept the controller to sample the three pulses of data bits 7, 8, and 9, and follow the principle of taking two out of three to determine the final value. The fundamental purpose of using this method is to enhance anti-interference and improve the reliability of data transmission. , the sampling signal is always in the middle of each receiving bit, which can avoid the edge distortion at both ends of the data bit, and also prevent the error caused by the incomplete synchronization of the receiving clock frequency and the sending clock frequency.
First review the data format of asynchronous serial communication:
Since in the idle state , the transmission line is in the logic " 1 " state, and the data transmission always starts with a start bit " 0 " , so when the receiver detects a transition from " 1 " to " 0 " , it is regarded as a possible start bit (to exclude the jump caused by interference) ; after the start bit is confirmed , it is known that the transmitter has started to send, and the receiver can receive subsequent data in this data communication format; when After the stop bit " 1 " is detected , it indicates that one frame of character data has been sent.
The most important point about the design of the receiver is how to improve the sampling accuracy. It is best to ensure that the sampling point is in the middle of the time of the sampled data . Therefore, the data should be sampled with a clock that is n times higher than the data baud rate (n ≥ 1) when receiving samples . Sampling is done with a 16x baud rate clock in this program . Combined with the diagram, let's explain how to make the sampling moment in the middle of the time of the sampled data:
1. If a low level is detected at time t1 , the continuous detection of this low level starts
2. When t2 is reached after 8 clock cycles are detected, at this moment, if the previous 8 cycles are all low level, it is considered that the start pulse has been detected. Otherwise, it is considered as interference and re-detection.
3. After the start bit is detected, count 16 more sampling clock cycles to reach the time middle point t3 of the first data bit, at which point the data is sampled and saved.
4. Then after 16 cycles, it is the time middle point of the second data bit, and sampling is performed at this moment; then, after 16 cycles, it is the time middle point of the third data bit, and sampling is performed at this moment. … .. keep sampling until all data bits have been sampled.