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FPGA is programmed based on SRAM, and the programming information will be lost when the system is powered off. Every time the system is powered on, the programming data stored in the FLASH or EEPROM outside the device needs to be rewritten into the internal SRAM. FPGA online loading requires the help of the CPU, and the CPU has been started and working before loading. The loading modes of FPGA mainly include the following: 1). PS mode (Passive Serial Configuration Mode), that is, passive serial loading mode. PS mode is suitable for FPGA loading occasions where the logic scale is small and the loading speed is not high. In this mode, the configuration clock signal CCLK required for loading is provided by the FPGA external clock source or external control signal. In addition, PS loading mode requires the support of an external microcontroller. 2). AS mode (Active Serial Configuration Mode), that is, active serial loading mode. In AS mode, the FPGA actively reads the logic information from the external storage device to configure itself. The configuration clock signal CCLK in this mode is provided by the FPGA. 3). PP mode (Passive Parallel Configuration Mode), that is, passive parallel loading mode. This mode is suitable for FPGA loading occasions with larger logic scale and higher loading speed requirements. In PP mode, the external device loads the FPGA logic through the 8bit parallel data line, and the CCLK signal is provided externally. 4). BS mode (Boundary Scan Configuration Mode), that is, the boundary scan loading mode. That is what we usually call the JTAG loading mode. All FPGA chips have three or four load mode configuration pins, and different load modes are selected by configuring MESL[0..3]. First, let's introduce the PS loading mode. There are some differences in the definition of PS loading ports for FPGA products of various manufacturers. The following is an introduction to the PS loading methods of the three mainstream FPGA manufacturers, Altera, Xilinx, and Lattice. The PS loading interface of Altera's FPGA products is shown in the figure below. 1).CONFIG_DONE： Loading completion indication output signal, I/O interface, active high, in actual use, pull up to VCC through a 4.7K resistor, so that the default state is high, indicating that the chip has been loaded, when the FPGA is loading, it will be driven low.
2).nSTATUS： Chip reset completion status signal, I/O interface, active low, when it is low, it means that it can receive loading data from the outside. In actual use, it is pulled up to VCC through a 4.7K resistor, so that its default state is high, which means that it does not receive loaded data.
3).nCE： Chip enable pin, input signal, active low, indicating that the chip is enabled. When nCE is at a high level, the chip is in a disabled state, and any operation on the chip is prohibited. For a single FPGA chip board, nCE can be directly connected to GND. For a multi-FPGA chip board, the nCE of the first chip is connected to GND, and the nCE of the next chip is connected to the nCEO of the previous chip.
4).nCEO： Enable output signal, when the chip is loaded, the output of this pin is low, and when the chip is not loaded, the output is high. For a single FPGA chip board, nCEO is left floating. For a multi-FPGA chip board, nCEO is connected to the nCE of the next chip.
5).nCONFIG： Start the loading input signal. When it is low, it means that the external request FPGA needs to be reloaded, reset the FPGA chip, and clear the existing data in the chip. In actual use, this pin is pulled up to VCC through a 4.7K resistor, making its default state high.
6).DCLK： Load data reference clock. Input in PS mode and output in AS mode.
7) .DATA0 Load data input, input signal.
8).MSEL[0:3]： Load mode configuration pins. Controls the loading mode.
That is what we usually call the JTAG loading mode. All FPGA chips have three or four load mode configuration pins, and different load modes are selected by configuring MESL[0..3]. First, let's introduce the PS loading mode. There are some differences in the definition of PS loading ports for FPGA products of various manufacturers. The following is an introduction to the PS loading methods of the three mainstream FPGA manufacturers, Altera, Xilinx, and Lattice. The PS loading interface of Altera's FPGA products is shown in the figure below.
1).CONFIG_DONE:
Loading completion indication output signal, I/O interface, active high, in actual use, pull up to VCC through a 4.7K resistor, so that the default state is high, indicating that the chip has been loaded, when the FPGA is loading, it will be driven low.
2).nSTATUS：
Chip reset completion status signal, I/O interface, active low, when it is low, it means that it can receive loading data from the outside. In actual use, it is pulled up to VCC through a 4.7K resistor, so that its default state is high, which means that it does not receive loaded data.
3).nCE：
Chip enable pin, input signal, active low, indicating that the chip is enabled. When nCE is at a high level, the chip is in a disabled state, and any operation on the chip is prohibited. For a single FPGA chip board, nCE can be directly connected to GND. For a multi-FPGA chip board, the nCE of the first chip is connected to GND, and the nCE of the next chip is connected to the nCEO of the previous chip.
4).nCEO：
Enable output signal, when the chip is loaded, the output of this pin is low, and when the chip is not loaded, the output is high. For a single FPGA chip board, nCEO is left floating. For a multi-FPGA chip board, nCEO is connected to the nCE of the next chip.
5).nCONFIG：
Start the loading input signal. When it is low, it means that the external request FPGA needs to be reloaded, reset the FPGA chip, and clear the existing data in the chip. In actual use, this pin is pulled up to VCC through a 4.7K resistor, making its default state high.
6).DCLK：
Load data reference clock. Input in PS mode and output in AS mode.
7) .DATA0
Load data input, input signal.
8).MSEL[0:3]：
Load mode configuration pins. Controls the loading mode.