| Signal name |
Paraphrase |
| DEV_OE |
I/O enable pin, the DEV_OE option can be enabled in QII. If this feature is enabled, all I/Os are tri-stated when DEV_OE is deasserted. |
| DEV_CLR |
Clear input to enable DEV_CLR option in QII. If this feature is enabled, all registers will be cleared when DEV_CLR is set low. |
| DIFF_n |
The n-terminal of the differential port. |
| DIFF_p |
p-side of the differential port. |
| DQ |
Bidirectional data bus. |
| DQS |
Bidirectional data control pin. |
| CLK_n |
Differential clock signal n terminal |
| CLK_p |
Differential clock signal p terminal |
| Other_PLL |
phase locked loop. |
| Other dual purpose |
Multi-purpose pins can realize different functions according to different constraints. |
| MSEL |
Program loading mode selection signal. |
| CONFIG_DONE |
Configuration end signal. |
| nCE |
Download chain device enable input, connected to the nCEO of the previous device. Ground nCE for the first device in the download chain. |
| nCEO |
Download chain device enable output. In a download chain, when the configuration of the first device is complete, this signal enables the next device to begin configuration. The nCEO of the last device in the download chain should be left floating. |
| nCONFIG |
User mode configuration start signal. |
| TDI |
Data input, data is input to the JTAG port through TDI. |
| TCK |
clock input. |
| ETC |
Mode selection. |
| TOD |
Data output, the data is output from the JTAG port through TDO. |
| nSTATUS |
Configure status signals. |
| VREF |
reference voltage. |
| VCCP |
digital power. |
| VCCR |
receive power. |
| VCCT |
Send power. |
| VCCA |
Analog circuit power supply. |
| VCCINT |
core voltage. |
| VCCIO |
I/O port voltage. |
| GND |
Signal area. |