Xilinx FIFO Generator needs to pay attention to asymmetric bit width
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In the use of FIFO, the asymmetric bit width is often involved, such as the input bit width 32 bitand the output bit width 64 bit;
Xilinx's FIFO IP supports similar operations (Altera's also supports).
However, some conditions are restricted. Before carefully reviewing the manual, it is impossible to assume that any ratio is supported.
From pg057-fifo-generator.pdf，Page114, the following information can be acquired.
Does it support
Whether the asymmetric ratio is supported is affected by different RAM types , as shown in the following table:
It can be seen from the table that Block RAM and Built-in type RAM support asymmetric bit width under the condition of independent clock and common clock, and others cannot;
Optional ratio
The asymmetric ratio is to allow FIFOthe depth of input and output to be different. The supported write and read ratios are:
1：8，1：4，1：2，1：1，2：1，4：1，8：1；
The ratio can Vivado IP Catalogbe selected through special options on the GUI interface that generates the FIFO (by default, it is 1:1);
The ratios from 1：8to to 8：1are all selectable, and the output depth is automatically calculated based on the input depth, bit width and read bit width.
Read and write operations
For asymmetric ratio FIFOs, FULLsignals and EMPTYsignals are only valid when a complete word (understood as a longer bit width) can be written or read.
FIFO does not allow partial words to be accessed .
For example, assuming a FULLFIFO in a state, if the write widthis 8 bitsand the read widthis 2 bits, 4 valid read operations should be completed FULLbefore the signal can be deasserted, so that the write operation can continue.
The write operation count displays the number of words in the FIFO according to the ratio of the write port (write bit width is the number of words), and the read operation count displays the number of words in the FIFO according to the ratio of the read port (take the read bit width as one The number of words);
1:4 ratio data sequence
The example in the figure below is a 1：4ratio FIFO (write width is 2 and read width is 8).
In the legend, a 4consecutive write operation is performed before the read operation . The first write operation is 01, the next is 00，11, and the last is 10.
The memory is filled from left to right (MSB to LSB). When a read operation is executed, the received data is 01_00_11_10;
The following figure shows the t of 1：4ratio FIFO din，douand some waveforms of handshake signals. After 4 words are written into the FIFO, the EMPTYsignal is deasserted . After a read operation, the EMPTYsignal resumes assertion .
4:1 ratio data sequence
The example in the figure below is a 4：1ratio FIFO (write width is 8 and read width is 2).
In the example, after the sequential write operation is performed, a 4read operation is performed again.
The data of the write operation is 11_00_01_11. When the read operation is performed, the data from left to right (MSB to LSB) will be received by the read data. As shown in the figure below, the first read out is recorded as 11, then 00，01, the last is 11.
The following figure shows the waveforms of the 4：1ratio FIFO din，doutand some handshake signals. After a write operation of one clock, the FIFO cancels the assertionEMPTY signal. Because no other write operations are performed, the FIFO resumes assertion after 4 read operations.
to sum up
When using asymmetric bit width ratio FIFO, you need to pay attention to the following two points:
- Whether the ratio is supported , only supports 1, 2, 4, and 8 magnification relationships;
- For the sequence of data reading and writing , it is necessary to determine whether the MSB and LSB of the data are consistent with expectations;
After it is recommended to instantiate the IP, do the recommended modelsim simulation first, and be familiar with the data transmission mode of the FIFO IP, handshake signals, and then design;