Xilinx FIFO Generator needs to pay attention to RST reset
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Record the problems encountered when using Xilinx's FIFO Generate (modelsim simulation and ILA can be encountered);
——full，empty Keep high when waiting for the signal;
direct cause
The following content all talk about Asynchronous Reset ;
There is an introduction in the manual pg057-fifo-generator.pdf, Page127 :
Poor translation:
When performing a reset operation, the read and write clock must be valid. Regardless of the reason, at the time of the reset operation, if the read-write clock is lost, the reset operation must be performed again at the time when the read-write clock is valid. Violating this operation will result in unexpected behavior. Even the signal busy will be stuck and the FPGA may need to be reconfigured.
other suggestion
There are also suggestions for asynchronous reset in the follow-up of the article:
Poor translation:
If the signal width of the asynchronous reset is a slow clock width (should be the slower one of the read and write clocks), and it is asserted very close to the rising edge of the full clock, then the reset detection may not encounter this cause Unexpected behavior occurs. In order to avoid this situation, although in this manual it is sometimes said to assert one cycle of the slow clock, it is generally recommended that the asynchronous reset signal assert at least three slow clock cycles.
There is a definition of C_SYNCHRONIZER_STAGE in the article. I don't understand what it means. If you know, you can comment on it.
Timing
The recommended reset sequence is also given in the manual:
Note: All output signals of the FIFO must be considered invalid during the No Access Zone in the figure ;
The timing can be observed:
- The RST signal has a high level of 8 slow clock cycles;
- During the rising edge of RST, after 7 wr_clk cycles, the WR_RST_BUSY signal is pulled high, and the FULL signal is pulled high. At this time, the wr_en signal should be pulled low;
- During the RST rising edge period, after 7 rd_clk cycles, the RD_RST_BUSY signal is pulled high, and the EMPTY signal is pulled high. At this time, the rd_en signal should be pulled low, and the data output ports at this time are all invalid;
- After reset cycle + 60 full clock cycles, FIFO can be read and written normally;
An unsafe timing diagram is also given in the manual:
The most obvious thing in this figure is that the reset cycle of Async Reset is 3 slow clock cycles.
This timing situation may cause some exceptions (but FIFO can still read and write after this timing).
simulation
In the timing of modelsim simulation, if the reset of the FIFO occurs before wr_clk or rd_clk, the FIFO cannot be read or written (note that the FULL signal and the EMPTY signal will be forcibly pulled high):
Then, reset the FIFO again, the FULL and EMPTY signals return to normal, and the FIFO can be read and written normally:
to sum up
Pay attention to the RST signal when using FIFO IP, it is recommended to meet:
1. A valid reset must be valid after wr_clk and rd_clk are valid;
2. A valid reset must maintain at least 8 cycles of the slow clock;
3. After the reset operation, it is recommended to wait at least 60 slow clock cycles before using the FIFO for read and write operations ；
According to these three conditions, configure the RST of the FIFO, and there is no problem at present. If there is any problem, comment and communicate.