Generally speaking, the current in our internal circuit is generally generated by modules such as bandgap. Of course, bandgap may have limited driving ability. It is usually equipped with a buffer at the back, and then a bunch of PMOS current sources are connected:
Fig.1 Current source, switch, and local circuit
For example, the remote bias gen in Fig.1 is assumed to be part of a certain buffer. After passing through the metal traces that are not known for how long (dotted lines) there are in the middle, finally came to a local module, such as an ADC. Of course, in order to turn this circuit from a long distance into a good current that the local people like to hear, some careful thoughts such as capacitors are usually added next to it. However, it looks roughly like the one drawn in the picture above.
Back to the topic, if we need to add controllable functions, for example, if we don't want to use this local ADC, we need a switch, and we can turn off this local bias gen at any time. This red switch is now drawn here. Do you have any ideas?
The normal switch is of course the transistor. So, how do you put this transistor on?
Fig.2 Intuitive local switch
Well, this is an intuitive idea. This M2 is what we need. But, why does it look a little bit that? If working under a low-voltage power supply, such as a typical process below 65nm, the VDD of CMOS is generally 1.2V. Assuming Vth is 450mV, let's do a little calculation:
The lower M1 is a diode connection, so the voltage above the drain of M1 is about 450+200=650mV (200mV is the normal overdrive voltage), and at the same time, this voltage is also the source voltage of M2. Generally, when M2 needs to be turned on, the gate of M2 is connected to the highest Vdd, which is 1.2V. In this way, Vgs of M2=1.2V-0.65V=0.55V.
Therefore, we think that M2 is a very good switch with a very large Vgs and works completely in the linear region. As a result, people's Vgs only had less than half the pitiful vdd. The world is so difficult, if you go to another ss corner and the vth is bigger, can this little poor M2 still be turned on? This is a problem……
In addition, because M2 may not be large enough vgs, but the current Id is limited by the remote current source. So, what should I do if there is not enough vgs? Rely on Vds! It is very likely that M2 will start to use its fists in desperation and go up and down to grab the Vds needed (Vds of M2 may be greater than 200mV, not a few mV as we thought) to meet the requirements of Id. Therefore, it is possible that the PMOS of our remote current source is pressed by M2 so that Vd has been rising, resulting in the stated current of 10uA, which has become 9uA or less. Tragedy!
To summarize: 1) The Vgs of M2 may not be enough; 2) M2 needs to conduct a certain current. When Vgs is not enough, Vds needs to increase, thus reducing the vds of the upper and lower transistors.
Now that the problem is known, what can be done to solve the problem?
Fig.3 Circuit after optimization
Change location!
The source of the trouble for the M2 in Fig.2 above is that in addition to behaving like a complete switch, which can be turned on or off normally, it also has to undertake a certain amount of current transport work. The former one can be regarded as a digital function, and the latter one can be regarded as an analog function. In other words:
Digital function: on/off of the channel;
analog function: strong or weak current delivery;
So, if we focus on one of the functions, that is, the key digital function, the structure of fig.3 is very practical. Here, M2 only controls the gate and drain of M1. Because there is basically no current on the gate of the CMOS transistor (leakage will not be discussed for the time being), in this way, even if M2 cannot perfectly achieve the maximum vgs (Vgs equal to 1.2V Vdd, such as most logic circuits), but at this time The M2 has no need to deliver current, even if it is equivalent to a large resistance, it will not affect the main path, that is, from the upper PMOS to the lower diode M1.
At the same time, sometimes we will add a capacitor to the gate of M1, which can also play the role of LPF to a certain extent. After all, the local bias gen in the back cares about the Vg generated by M1!
But! Finally, I remembered one thing: if you want to turn off M1 completely when power off, M2 in Fig.3 may not be enough! The M1 of a floating gate always sounds a little frightening... Then add a power off switch to the M1 gate! That is M3. The control signal of M3 is opposite to that of M2 , so when M2 is disconnected, the gate of M1 can be pulled to vss to prevent the residual charge on the gate of M1 from causing unnecessary trouble.
PS: A colleague in the comment said that it can be like this:
The advantage of Fig.4 is that Vgs of M2 is equal to Vdd, which ensures that M2 will be fully on. (Unlike the Vgs of M2 in Fig.3, it may not be enough.) However, in order to make the source of M1 not too large (the source of the following circuit is connected to vss, so the source of M1 is best to be Vss. Just now. Commenting on matching, the author added an M4, anyway, do not use the gate voltage of M1 in the subsequent circuit, regenerate it!) The size of M2 is better . so, a little wasted area...
In other words, for a simple switch, the author Jun La Li Lao has written so much, he is a bit disgusted... In fact, the author feels that as a true engineering discipline, it is really necessary to consider everything. Sometimes a little bit of a problem may be magnified by countless times during actual mass production. Everyone must be cautious!
Two people in the comments have already mentioned this structure, let me say one more thing:
Fig.5 Structure not recommended.
It is true that M2 is similar to cascode. Under the premise that there is no M3, the source of M2 is the drain of M1. Compared with the structure of fig.2, M2 is easier to conduct. but! It is necessary to add M3, so, M3 when M2 is off, and the current source above flows along M3 to vss. This kind of leakage is not what we want to see...