Configuration steps:
(1) Enable timer and output pin clock (if remapping is used, enable AFIO clock).
(2) Initialize GPIO. If there is no remapping and only multiplexing, then configure according to 8.1.11. If there is remapping, turn on remapping. E.g:
Remapping is fixed. For example, if you enable partial remapping of TIM3 in the above figure, we must enable remapping after we are sure to use PB5 or PB4.
(3) Configure the clock source and time base unit of the timer to be used:
Note : If we use the internal clock CK_INT as the clock source, we should pay attention to a sentence in the manual: " The CK_INT clock here is multiplied from APB1. In STM32, unless the clock division number of APB1 is set to 1, the general timing The clock of the TIMx is twice the clock of APB1. When the clock of APB1 is not divided, the clock of the general timer TIMx is equal to the clock of APB1 ."
(4) Initialize pwm output comparison parameters: see appendix 2
①Select pwm output mode.
Output mode 1: It is valid when the value of the counter is less than the value of the comparator (no matter it is counting up or down).
Output mode 1: It is valid when the value of the counter is greater than the value of the comparator (whether it is counting up or down). )
②Select the output polarity
to set the effective signal to output 1 or 0
③Enable the output of the corresponding channel (corresponding pin)
④Set the comparison value
(5) Set the automatic reloading of the time base unit and the automatic reloading of the compare register
Note : How to understand the ARPE bit of the counter (how to understand the automatic reload):
If the original value of ARR is 300, modify it to 100: When
ARPE writes 0, there is no buffer, and it is directly written to the shadow register. CNT overflows when it reaches the new value of 100 this time.
When ARPE writes 1, it waits until CNT reaches the original value of 300 to overflow, then writes to the shadow register, and the new value of 100 overflows next time.
(6) Enable the corresponding timer
(7) Through the library function TIM_SetCompare1(); operate the register CCR1 to change the comparison value to change the duty cycle, see Appendix 1.
Note: The cycle (or frequency) of the PWM output is related to the counter of the time base unit, and the duty cycle of the PWM output (that is, the time ratio of the positive level in a cycle) is related to the value of the comparator.
Attached 1. PWM working process
Attached 2. Corresponding registers
The supplement of advanced timer:
http://www.openedv.com/posts/list/28659.htm
Generally, high-power motors, frequency converters, etc., at the end are all H-bridges or 3-phase bridges composed of high-power tubes, IGBTs and other components. **The upper and lower half bridges of each bridge cannot be turned on at the same time. **However, when the high-speed PWM drive signal reaches the control pole of the power element, it is often delayed due to various reasons As a result, a certain half-bridge component is not turned off when it should be turned off, causing the power component to burn.
(1) What is a dead zone?
The dead zone is to delay the opening of the lower half bridge after the upper half bridge is turned off for a period of time, or to delay the opening of the upper half bridge for a period of time after the lower half bridge is turned off, so as to avoid the burning of the power components. This delay time is the dead zone.
Methodology: Therefore, designing a PWM wave with a dead zone can prevent the upper and lower devices from being turned on at the same time. In other words, when one device is turned on and then turned off, it passes through a dead zone before the other is turned on.
(2) What is the brake function?
This is actually used to stop the PWM output. Because it is often used in motor control, it is called brake, break, and it seems more appropriate. When faults or other reasons are detected, the motor can be stopped immediately to improve safety.