1. The best host-what is Scala
"If I were to choose a language other than Java today, I would choose Scala."-James Gosling, the father of Java
Among the many programming languages today, Java is often the language of choice for software developers. And Scala, which allows the father of Java to give such an evaluation, must have its appeal. So, what kind of language is Scala?
Scala is a language that runs based on JVM (Java Virtual Machine), and it is compatible with Java. At the beginning of the design, seamless connection with Java is considered, and the two can call each other. But the purpose of its designers is to create a language that is more usable, more efficient, and better than Java. In terms of operating mechanism, Scala will be compiled into the same bytecode as Java and run by the JVM, so the program speed is as fast as Java. From a practical point of view, its form is much more concise than Java, its syntax is more powerful, and the amount of code is often much less than that of Java with the same function. Although this is still a niche language, you might as well try to learn it.
Scala is an object-oriented functional language. Today, object-oriented has become an indispensable attribute of programming languages, and its power does not need to be explained too much. But on the other hand, Scala did not choose the imperative programming style that more people are familiar with, but chose a more niche functional programming concept. For readers who are familiar with popular languages such as C/C++, Java, Python, etc., they may never have been exposed to functional programming. Please stay calm, only need basic learning, readers will be able to master basic functional programming, and will gradually discover the beauty of functional programming. Scala encourages users to use functional programming, but it also leaves room for imperative programming.
Just like the "Scalable" from which its name is taken, this is also a language that can be scaled freely: it can both tailor existing class libraries and extend custom class libraries; it can be used to complete a simple script and is sufficient Competent for any complex and huge software system. Its syntax is more concise than Python, and its abstraction ability is more advanced than C++. Because of this, the learning curve of Scala is not smooth, but stair-like. For this reason, if you can learn Scala patiently, gradually master the advanced grammar it provides, and deeply understand its programming concepts, then you will find that this is likely to be a programming language that you can't put it down and meet each other late.
Scala's biggest advantage may be its strong scalability created by its various grammatical conveniences, and then it becomes an excellent host language. In other words, developers can easily use a custom Scala library to quickly develop a "new" language specifically for a particular purpose. At present, it is recognized as the best host language for constructing DSL (domain-specific languages) (this remains to be verified).
2. Agile development-what is Chisel
As far as every digital circuit engineer is concerned, Verilog can't be more familiar, and may have been unable to complain. It is true that Verilog is still a product of the C language era. Nowadays, the problem of low development efficiency is becoming more and more obvious. Software development efficiency has already improved by leaps and bounds in other languages, transistor density has also risen in line with Moore's Law, and our front-end HDL language seems to be still in place. As early as 20 or 30 years ago, people thought that Verilog/VHDL was going to be obsolete. Developers at that time were mainly divided into three groups: one group advocated that Verilog should be improved, and the other two groups advocated language transfer to software language (the other group advocated C++, One group advocates Java), so that you can get open source synthesis tools and emulators. In the end, the improved version of Verilog won, which is the follow-up standard of Verilog-SystemVerilog. On the one hand, people who support the improvement of Verilog accounted for the majority; on the other hand, they also got support from Intel.
However, SystemVerilog is not very easy to use. First of all, although it introduces object orientation, it can only be used for verification, because verification is more like software than hardware design. Secondly, SystemVerilog solves some Verilog syntax flaws, making hardware design more convenient, but the effect is not obvious, and it is not a cure for the symptoms. Furthermore, EDA vendors' support for SystemVerilog is not active enough, and not all new features have been implemented up to now, making the industry still prefer to adopt Verilog-2001. To sum up, from Verilog to SystemVerilog, there is not such a huge leap from C to C++.
What about the C++ group? It is the SystemC that we are now familiar with. In fact, SystemC is a bunch of class libraries defined in C++. Most of the development of SystemC is still used at the transaction level, that is, writing hardware models. It is rare to use SystemC to develop hardware directly, because the current EDA tool support is not good enough. Compared with Verilog, the developed circuit is poorly optimized.
What about those who advocate Java? It seems that we are only now seeing the appearance of the HDL language based on the Java platform-Chisel, although Scala is not Java, but based on JVM. Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language developed with Scala as the host language. It is a new type of hardware language released by the research team at the University of California, Berkeley. According to one of the team members, Professor Krste Asanovic, they had already begun to conceive of such a language when there was no hardware description language more than 30 years ago. At first Chisel was based on Ruby, but later I found that Scala is more suitable for building Chisel. Because Scala has many characteristics suitable for describing circuits, for example, it is a static language, mainly at compile time, and suitable for conversion to Verilog/VHDL. For example, its operators are methods, currying, pure object-oriented, powerful pattern matching, convenient generic writing, trait mixing, functional programming and other characteristics, which make it very convenient to develop DSL language in Scala. The firrtl compiler can convert Chisel files into firrtl files. This is a standard intermediate exchange format, which is a medium that allows various high-level languages to be easily converted to Verilog/VHDL, but it is actually at the same level as verilog/VHDL . Here, Chisel chose to compromise, instead of directly generating the circuit, but relying on Verilog, mainly because there is no EDA tool support, so it is not equivalent to HLS (High Level Synthesis). In the future, there may be EDA tools that directly support Chisel.
Chisel solved some of Verilog's pain points. First and foremost, that is, the introduction of object-oriented features in the hardware circuit design. Secondly, a lot of unnecessary grammar is reduced, and flawed grammar is improved. Verilog was originally intended for circuit verification, not design, so there are many unsynthesizable grammars. In the process of converting Chisel to Verilog, these non-synthesizable grammars will not be used, so there is no need to worry about not being able to generate circuits when writing Chisel, which is a great convenience for hardware novices. For another example, Verilog's reg does not necessarily refer to a register, which is often misunderstood by novices, while Chisel's Reg is a register, which has no ambiguity. Finally, using Scala's features such as pattern matching, trait mixing, and class inheritance can quickly change the circuit structure. For the increasingly large SoC system, this is very important.
The original intention of designing Chisel is because the Berkeley team has only a dozen members. Compared with the configuration of hundreds or thousands of engineers in conventional hardware design companies, this is really "bad". However, with the help of Chisel, they completed the successful tape-out from the RISC-V instruction set design to the Rocket chip in only one year and $1 million. This has to make people wonder, how magical is Chisel's "chisel" (Chinese meaning)?