A simple example: At first there are two two .c and .h files (hannuo.c not without tube)
test.c:
test.h：
txt.c：
txt.h：
Files in the same directory:
Under normal circumstances the compiler:
We can see the result successfully generated file, execute:
Now is achieved by writing the Makefile:
First create a Makefile file (before I built the above, there is no need to build a name must be a Makefile or makefile), then the file is written in vim.
The first to write dependencies, compile write commands (commands must start with the tab key, where the target filename positioning result, you can customize)
-------------------- -------------------------------
the Result: test.o txt.o
gcc -o the Result test.o txt.o
the Test .o: test.c
gcc -c test.c
txt.o: txt.c test.h txt.h
gcc -c txt.c test.h txt.h
------------- --------------------------------------
such a simple Makefile file on the production well, then down and returned to the terminal, enter the make command can generate a result file, run it successfully. (Following the original first generation result to delete, copy the code before the Paste command instead of the tab key to change it)
Makefile:
Delete result:
result:
The above wording is one of the most primitive, the string may be written in simplified substitute.
operation result:
Explanation: "=" Equivalent behind the front, with the $ () to reference the same format, Clean: compile command to clear the generated file, $ (obj) which generates a .o file, result may be generated i.e. executable file, after clearing below.
There wording:
operation result:
Which .gch precompiled header files, speed up compilation
Here there is more concise wording:
operation result:
Here, we use several special macros. % .O:.% C, which is a regular pattern, indicating that all of the .o object depend on its .c file with the same name (also listed in the header file head), $ ^ represents all dependent relationship here namely .c and .h file, $ <represents the first term dependency, namely .c file, but here is useless to just tell us. If .o or other documents will look too simple and not enough long list, you can add functions to write to make it more convenient, as follows:
or
Which, shell function is mainly used to execute shell commands (terminal commands) ./ that is in the current directory, you can change the path to your program files directory to find the specific here is to find all .c and .h in the current directory file. The $ (source:..% C =% o) is a character replacement functions, it will source all the strings replaced with .o .c, that is, all the .o files, so no matter how much we join in the project .c and .h files Makefile will automatically be included in the project, the need to add manually is extremely easy, and no matter how many other documents generated commands are available to make clean once cleared, restored to its original state. All income must be less than the above-mentioned study, if the error also requested comments or suggestions!