MSP432P401R clock system

MSP432P401R clock system

MSP432的时钟模块(CS),个人理解msp432最特色的功能应该是超低功耗和高性能的组合。432系列的时钟系统主要有三个方面:

  • 1. Hardware clock-clock source; basic
  • 2. Clock mapping-control conversion; conversion
  • 3. Clock setting-software control; configuration

1. Clock source:

1.1 LFXTCLK: external low frequency clock source, generally 32.768kHz crystal oscillator or external clock
1.2 VLOCLK: Internal low-power low-frequency clock, 9.4kHz
1.3 REFOCLK: internal low-power low-frequency clock, 32.768kHz or 128kHz
1.4DCOCLK: Internal adjustable digital clock, typical value 3MHz
1.5 MODCLK: internal low-power clock, typically 25MHz
1.6 HFXTCLK: external high frequency clock, 1MHz–48MHz, can be crystal oscillator, external always, when bypassing, you can use external square wave signal SYSOSC internal clock, typical value 5MHz

2. System clock-control conversion:

  • 2.1. ACLK: auxiliary clock, optional LFXTCLK, VLOCLK, REFOCLK, up to 128kHz, can be divided, mainly used for low-frequency peripheral MCLK:
  • 2.2. System main clock, optional LFXTCLK, VLOCLK, REFOCLK, DCOCLK, MODCLK, HFXTCLK, can be divided, can be used for CPU and peripherals, HSMCLK:
  • 2.3. Subsystem master clock, optional LFXTCLK, VLOCLK, REFOCLK, DCOCLK, MODCLK, HFXTCLK, can be divided, can be used for high-speed peripherals
  • 2.4. SMCLK: Low-speed subsystem main clock, obtained by dividing by HSMCLK, optional LFXTCLK, VLOCLK, REFOCLK, DCOCLK, MODCLK, HFXTCLK, up to half of the highest clock of HSMCLK, can be used for peripherals BCLK: low-speed backup clock, optional LFXTCLK, REFOCLK, up to 32kHz
Clock control try to use low frequency clock
Each clock can be turned on and off individually
The clock works in different power modes

3. Register function-software setting register

CSKEY: CS module key register, the correct key must be written in before the CS module can be operated
CSCTL0: CS control register 0, DCO control register, used to control DCO enable and frequency setting
CSCTL1: CS control register 1, SMCLK, ACLK, HSMCLK, MCLK frequency division and clock source selection, BCLK frequency division
CSCTL2: CS control register 2, LFXTCLK, HFXTCLK configuration register
CSCTL3: CS control register 3, LFXTCLK, HFXTCLK error count configuration register CSCLKEN: clock source and system clock enable register CSSTAT:
Clock status register CSIE: clock error, error count interrupt enable register CSIFG: interrupt flag register
CSCLRIFG: interrupt clear flag register CSSETIFG: interrupt setting pending register CSDCOERCAL0: DCO external resistance calibration register 0
CSDCOERCAL1: DCO external resistance calibration register 1

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Origin blog.csdn.net/qq_43694114/article/details/108562300