1. VCS simulation process
Step1: Compliation
Verilog Code (cpu.v)-simv (Simulation Executable)
Step2: Simulation
simv-FSDB Files (VPD Files / VCD Files)
Verdi Debug can be used later.
2. VCS simulation mode
2.1 Two steps of vcs simulation:
code compilation: such as vcs cpu.v
simulation operation: such as simv
or the -R option to synthesize the two steps into one step:
compile and run: such as vcs -R cpu.v
2.2 There are 2 kinds of vcs simulation operation Method:
interactive mode, interactive mode,
batch mode, batch mode,
interactive mode is divided into two types, namely, CLI interface and GUI interface.
CLI Command Line Interface interface: text
% vcs cpu.v + cli + 3 -R -s The
common practice is to write the CLI command into a script file, which is called by the include option when vcs is compiled, such as:
% vcs cpu.v -R -s -include script_file
or
% vcs cpu.v -ucli -R -s
ucli> source script_file
GUI Graphical User Interface: Virsim
% vcs cpu.v -RI // Compile to generate an executable file, start Virsim
post-processing debugging mode immediately : Run VCS simulation, DUMP the simulation result data into the waveform, and analyze the waveform through tools such as Virsim, DVE or Verdi
% vcs cpu.v -R -PP
% virsim
3, VCS simulation waveform
FSDB
initial
begin
$fsdbDumpvars(0,tb_top);
$fsdbDumpfile(“test.fsdb”);
$fsdbDumpflush;
end
VCD
initial
begin
$dumpvars(0,tb_top);
$dumpfile(“test.vcd”);
$dumpflush;
end
VPD
initial
begin
$ vcdpluson (0, tb_top);
$ vcdplusfile (“test.vcd”);
$ vcdplusflush;
end
4. VCS simulation options
The ones with-are generally used in compiling, and the compiling tools come with them.
The ones with a + sign are generally added by plug-ins, environments, verification languages, etc., and can be extended and customized.
vcs compile option
-cm <option>: specify the type of coverage, including: line, cond, fsm, tgl, path, branch, and assert
-cm_count: based on whether statistics are covered, further count the number of coverage
-cm_dir <directory_path_name >: Specify the storage path of the coverage statistics, the default is simv.cm
-cm_hier <filename>: specify the coverage statistics range, you can specify the module name, hierarchical name and source files, etc.
-cm_log <filename>: specify save coverage The name of the
resulting text file | -cm obc: enable observable coverage compilation
-comp64: compile the design in 64-bit mode, generate a 64-bit executable file for 64-bit mode simulation
-debug /- debug_all: Enable UCLI command line
-f < filename>: Specify the file name of the file list, the file may include the path name of the source code file, and the compile option parameters.
-f uses absolute paths; -F supports relative paths, but nesting is not allowed. When VCS uses -F to parse a filelist, nesting is not allowed, and include XX.v is not supported.
-file filename: similar to -f, can include PLI options and object files, can use escape characters, etc.
-full64: Compile in 64-bit mode to generate an executable file for 64-bit mode simulation, for 64-bit operating systems
-h / -help: List the parameters of commonly used compilation options and running options
-I: Compilation in interactive mode
-l < filename>: Specify the log file name of the vcs compilation and running information
-line: enable single-step operation in
VriSim -Mdir = <director>: specify a directory for VCS to store the files generated by compilation, the default is csrc
-Mlib = <director>: Specify a directory to let VCS search whether a module needs to be recompiled
-Mupdate [= 0]: incremental compilation, (-Mupdata = 0, keep the last makefile)
incremental compilation, only compile the changed files when compiling again, Increase the rate.
-noIncrComp: disable incremental compilation
-notice: display detailed diagnostic information
-o <name>: specify the name of the executable file generated by compilation, the default is simv
-timescale=<time_unit/time_precision>: Specify the timescale
time_unit for the source file compiled before and without `timescale. Use the nearest principle. For example, after the timescale is defined in the top file and the timescale is defined again in the intermediate file, the subsequent files will be executed according to the timescale defined in the intermediate file.
time_precision uses the smallest precision.
-override_timescale = <unit> / <preciision>: let the source file use the specified timescale
uniformly -pvalues + <parameter_name> = <value>: change the value of the specified parameter
-parameters <filename>: change the value of the parameter through the file, the parameter The path and changed value are defined in the file
-q: quiet mode Quiet mode, shielding VCS compilation information
-R: Executable file executed immediately after compilation
-s: Stop immediately at the beginning of simulation, and enter interactive mode. Generally used in conjunction with -R and + cli,% vcs cpu.v + cli + 3 -R -s
-V: enables verbose mode, Verbose mode prints the instructions of C Complier assembler and linker executed by vcs during operation
You can set the level of verbose UVM printing in scripts, + UVM_VERBOSITY = UVM_MEDIUM
-v < filename>: Specify verilog library file
-y < dir_pathname>: Specify the verilog library path
+libext+< extension>: Let VCS search for the specified extension file under the verilog library path, cooperate with -y
+ cli + [<module_name>] 1 | 2 | 3 | 4: enable CLI debugging function
+define+< macro_name>=< value>: Define a text macro to cooperate with ifdef in the source file
+incdir+< directory>： Specify the directory of the include file specified by search include, you can use “+” to define multiple directories
+ nowarnTFMPC: shield the “Too few module port connections” warning message during compilation
+ prof / + profile: generate a vcs.prof file, Record the module level that consumes the most CPU time during simulation.
+ nospecify: mask the path delay and timing check in the specify block + notimingcheck: mask the timing check in the
specify block
+v2k: Support Verilog-2001 standard
+vcs+lic+wait: Always wait for licese
+ warn = [no] ID | none | all: enable or disable the alarm information
-ntb: enable ntb (Native TsetBench), support Open Vera to verify the platform language structure
+ ntb_random_seed: set the seed of random variables vcs provides + ntb_random_seed_automatic.
-ntb_opts: If class is defined in module, -ntb_opts dtm option is needed for simulation.
-ntb_opts uvm-1.1 Add UVM library in VCS.
VCS operation options
-Sverilog: Support SystemVerilog
-ucli: enable UCLI command
Options for accelerating VCS simulation speed
Use + rad compilation option
Use + 2state compilation option
Use -Mupdate for incremental compilation
Use + nottimingcheck to mask timing check and minimize the generation of log files (such as -a and -l options).
Use post-processing debugging mode , Reduce debugging switches, try not to use breakpoints.
Use the + prof option to generate the vcs.prof file, view the CPU time at each module level, and determine the simulation bottleneck.
