PYNQ (ZYNQ) GPIO: MIO, EMIO, AXI_GPIO code for the lighting pynq EMIO

GPIO

MIO, EMIO ps is the



GPIO control and status register base address:0xE000_A000We SDK software operation under all operating to the underlying memory address space.

xparameters.h
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF

1) MIO 的 GPIO

PS is an I / O pin, the pin is fixed, does not consume resources when using PL
corresponding to BANK is BANK0, BANK1.

• After the other functions using the remaining MIO can be used as GPIO. It can be used inGPIO、SPI、UART、TIMER、Ethernet、USBEtc. Functionally, each pin has multiple functions at the same time, it is calledMultifunction
• This is FIXIO corresponding fixed pin, the pin does not need to user constraints.
• PS realize just rely on parts, namely the use of PL can not be configured. Without hardware configuration, software programming directly using the SDK.The operation can be seen as pure PS.
• A total of 32 + 22 = 54,
• Number in the SDK is 0-53.

2） EMIO的GPIO

EMIO still belongs to PS, but is connected to the PL, then the output signal from the PL.
Expandable by PL necessary to assign pins use, resource consumption when using PL pin. When MIO is not enough, PS PL may be part of the control pin by driving EMIO.
Corresponding BANK1 and BANK2,

• These IO are not multiplexed, and may be connected to FPGA pin, may be connected to an external FPGA logic, is very flexible extension,
• Its implementation relies on PS and PL system is complete. A total of 32 + 32 = 64,
• Corresponding to the number within the SDK from 54-117.

3) AXI_GPIO nuclear

IP core is encapsulated, PS M_AXI_GPIO achieved by IO interface control section PL, the consumption of resources and logical resources pin use.

register

1), DATA_RO register read port value.
2), DATA is the data output register.
3), DIRM, OEN are direction control register and output enable register.
4), MASK_DATA_LSW each BANK low output control 16, including a mask bits and data bits. (Note that overlapping functions and DATA)

CODE

PYNQ MIO no direct led, first test EMIO

CONSTRAINT

##Switches

set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_0_tri_io[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0]
#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1]

##LEDs
set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_0_tri_io[1] }]; #IO_L6N_T0_VREF_34 Sch=led[0]

SDK

Import example

int main(void)
{
	int Status;
	u32 InputData;
	XGpioPs_Config *ConfigPtr;


	printf("cccc");
	//my_gpiops_wr(0x204,v);
	
	printf("GPIO Polled Mode Example Test \r\n");
//load gpio
	ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
					ConfigPtr->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	//load gpio_R
		ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
		Status = XGpioPs_CfgInitialize(&Gpio_r, ConfigPtr,
						ConfigPtr->BaseAddr);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}





	//in
    XGpioPs_SetDirectionPin(&Gpio_r, 54, 0);
    XGpioPs_SetOutputEnablePin(&Gpio_r,54, 0);


	//out
	XGpioPs_SetDirectionPin(&Gpio, 55, 1);
	XGpioPs_SetOutputEnablePin(&Gpio, 55, 1);//Output_Pin
	while(1)
	{
		//InputData=XGpioPs_ReadPin(&Gpio_r, 54 );
	    InputData=XGpioPs_ReadPin(&Gpio_r,  54);
		XGpioPs_WritePin(&Gpio, 55, InputData);
	}