MPSOC family of processors is Xilinx introduced a new generation of integrated SOC, known as 5 times higher than ZYNQ series performance. Compared with ZYNQ, MPSOC most prominent is integrated 4CORE A53 / 2 core R5, GPU , H264 , etc., in graphic image processing, intelligent algorithms compare a greater competitive advantage. In addition, the interface also MPSOC great advantage, in addition to the ACP ZYNQ port, and no other cache coherent interface, and provides a CCI MPSOC bus, A53 / R5 / GPU / DMA and the like connected to the CCI can efficiently synchronize data bus, instead of the cache for special operations, which greatly improves the efficiency of data handling. This article uses Mill MYD-CZU3EG development board practical operation, GPIO drawn through the EMIO describes how, D37 and D41, and control flashing in the SDK.
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开发环境：vivado 2017.4，开发板型号：米尔MYD-CZU3EG， 主芯片XCZU3EG-1SFVC784。这个系列板子还有4EV，5EV等版本，手里的3EG版本不支持SFP,因此板上相应接口（白色部分）是空贴的。Generated vivado project (if you do not know how you can refer to the previous generation of engineering)
Step1 New Block Design
Click OK
Step2 add and configure the IP core PS
Click on the Add IP to add an IP core
Enter mpsoc, and then double-click Add Zynq UltraScale + MPSoC nuclear mpsoc
Nuclear shown below zynq mpsoc
Double-click zynq mpsoc nuclear import profile
Presets -> Apply Configuration
Here are importing a configuration file gpio_emio.tcl
After the configuration, as shown in FIG.
Right click and select Make External pin on gpio
gpio lead pin as shown below
Step3 generate comprehensive document 
Step4 generation FPGA top-level file
Step5 add xdc pin constraint
选择Add Create Constraints
Select Create File
Add a gpio_emio.xdc file
Click Finish
We offer a copy of the project inside the xdc file to the file gpio_emio.xdc
Step6 generate bit file
Step7 export the hardware configuration file
click on the menu bar File-> Export-> Export Hardware-> OK to export hardware profile
Step8 start the SDK, new fsbl
click on the menu bar File-> Launch SDK-> OK to start SDK
Click FileApplication Project New Project
Enter project called fsbl
Select Zynq MP FSBL
Generated as shown fsbl
Step9 a new project gpio_emio
click FileApplication Project New Project
Enter the project name gpio_emio
Select project template hello_world
New gpio_emio after completion, as shown below
Copy gpio_emio we provide engineering program to this project template hello_world
Step10 generate BOOT.bin file
right click gpio_emio -> Create boot Image
Click Create Image, boot files generated BOOT.bin
Copy this file to the SD card BOOT.bin
Development board mode setting, where we start mode is set to SD card
12V power development board, uart serial connection, the SD card is inserted
Development board to run electricity, two LED flash simultaneously