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We get two weeks to finally start the process 28335, registers and interrupt with a comprehensive understanding of the scale of mapping methods, such as memory division, today to see long-lost LED lights flashing, Dayton sweep haze. Especially in this summary under 28335GPIO external interrupt configuration and presentation. In fact, for a microcontroller, as long as these two functions can be achieved independently, it can be considered a beginning.
A, the GPIO port introduces
external binary information (digital) to be processed by the CPU, to give the memory storage, it is necessary to exchange the interface between both the outside information sources, if such a switching interface for performing general purpose digital input output, is called universal digital input / output interface, referred to as GPIO. F28335 DSP GPIO port as many as 88, 88 corresponding to the pins of the chip leads, and the package size is determined as the chip, the number of pins is limited, so that most of the 88 pins are multiplexed with the function that can be flexibly configured as an input pin, may be flexibly configured as an output, i.e., can be used as general purpose I / O pins, can be used as the special function port (e.g., SCI, SPI, ECAN, etc.), it is very flexible, according to user necessary, by GPIO MUX (multiplexer input and output, a multiplexing switch) related to the configuration register.
F28335DSP these GPIO port 88 is divided into A, B, C of the three groups, A group comprising GPIO0 to GPIO31, group B comprises GPIO32 to GPIO63, Group C GPIO64 to GPIO87, each pin is multiplexed with the plurality of functions the same time, each pin can only be a function of the pin. What working mode in which, each pin can be arranged through the GPIO Mux (multiplexed switch) register specific functions (universal digital I / O or peripheral special function). If these pins to select the digital I / O mode, the direction register is arranged GPxDIR digital I / O can be prepared by, i.e. as input or as an output pin; may also be quantized input signal by quantizing register GPxQUAL restrictions, thereby eliminating the digital I / O pins noise.
Two, and the GPIO port function register
1, register can be independently read by GPxDAT / write I / O signal; (slower operation, need to add a delay (without inversion), the following methods without additional delay)
2, using a register write GPxSET (invalid write 0) to I / O port for the set
3, using 1 GPxCLEAR register write (0 invalid write) to I / O port is cleared;
4, the register is set to 1 by using GPxTOOGLE (0 invalid write) to the I / O output level is inverted, the original high into low, had low to high level.
Set the GPIO module is made primarily by three registers (TI library file to the GPIO registers are divided into three parts, the actual register in these three categories) are: control register, data registers, interrupt register. (TI has defined three such names)
extern volatilestruct GPIO_CTRL_REGSGpioCtrlRegs;
externvolatilestruct GPIO_DATA_REGSGpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
Want to operate a peripheral, you can view the first several structure variables corresponding to the peripheral header files define last, in fact, several of these structures assignment. And then view the corresponding elements of structure, described later has a corresponding layer can then view the structure and elements contained in the notes behind readily appreciate the appropriate means, and then disposed can be required.
例:GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // GPIO2 = output
1, the control register
GPxCTRL; // the GPIO X the Register Control (to 31 is of GPIO0)
// set the sampling window period T = 2 * GPXCTRL * Tsysclk;
GPxQSEL1; // the GPIO X Qualifier the Select the Register. 1 (of GPIO0 to 15) (32-47)
GPxQSEL2; // the GPIO 2 X Qualifier the Select the Register (to 31 is GPIO16) (48-63)
// controls a pin for every two, determining the sampling period is 3 or 6 or sampling period without sampling
GPxMUX1; // the GPIO. 1 the Register Mux X (of GPIO0 to 15) (32-47) (64-79)
GPxMUX2; // the GPIO 2 X Mux the Register (to 31 is GPIO16) (48-63) (80-95)
// configuration function of each pin, 0: I / O functions, 1: peripheral functions.
The GPxDIR; // the GPIO the Register the Direction X (to 31 is of GPIO0) (32-63 of) (64-95)
// configure each pin is an input or an output, 0: digital input; 1: digital output.
GPxPUD; // the GPIO X the Pull Up the Disable the Register (to 31 is of GPIO0) (32-63 of) (64-95)
// enable or disable internal pull-0: the pull-on, 1: disable the pull
2, the data register
GPxDAT ; // GPIO Data Register (GPIO0 to 31) (32-63) (64-95)
GPxSET;//GPIO Data Set Register (GPIO0 to 31)(32-63)(64-95)——置位
GPxCLEAR;//GPIO Data Clear Register (GPIO0 to 31)(32-63)(64-95)
GPxTOGGLE;//GPIO Data Toggle Register (GPIO0 to 31)(32-63)(64-95)—反转
3、中断寄存器
GPIOXINT1SEL;// XINT1 GPIO Input Selection
GPIOXINT2SEL; // XINT2 the GPIO the Input Selection
GPIOXNMISEL; // XNMI_Xint13 the GPIO the Input Selection
GPIOXINT3SEL; // XINT3 the GPIO the Input Selection
GPIOXINT4SEL; // XINT4 the GPIO the Input Selection
GPIOXINT5SEL; // XINT5 the GPIO the Input Selection
GPIOXINT6SEL; // XINT6 the GPIO the Input Selection
GPIOXINT7SEL; XINT7 the GPIO the Input Selection //
the GPIOLPMSEL; // the GP Low Power Modes the I / O INPUT SELECT
can GPIO0-63 external interrupt setting;
other: sampling frequency: frequency divided into synchronous and asynchronous frequency
Synchronizing frequency: When the IO port IO as normal, the signal is sampled using sampling synchronization signal, or SYSCLKOUT SYSCLKOUT / n
Asynchronous Frequency: when the IO port such as the port outer peripheral SCISPI eCAN I2C, sampling frequency synchronization is not required, the peripheral asynchronous sampling frequency itself.
When a system reset, all pins are inputs default state, default IO port are common, as are the default sampling frequency SYSCLKOUT. Pull-up resistors except when reset ePWM (GPIO0 ~ GPIO11) are the default has been pulled up.
Sampling times:
Sampling window 3 times and six times two kinds of windows for filtering noise. 3 is a sampling window interval is two sampling periods, the sampling interval of the window 6 is 5 sample periods.
Only the signal collected during this sampling period 2 or 5 was exactly as described stable signal, the signal will be transmitted to the DSP, to sequentially eliminate noise.
(The sampling frequency and the sampling frequency with the actual requirements of use)
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 2; // XINT2 Qual using 6 samples
GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0x80; // Each sampling window is 128*SYSCLKOUT
GPIO register (A):
The above structure for the table of contents by TI following conversions:
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A ControlRegister (GPIO0 to 31)
union GPA1_REG GPAQSEL1; // GPIO A QualifierSelect 1 Register (GPIO0 to 15)
union GPA2_REG GPAQSEL2; // GPIO A QualifierSelect 2 Register (GPIO16 to 31)
union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register(GPIO0 to 15)
union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register(GPIO16 to 31)
union GPADAT_REG GPADIR; // GPIO A DirectionRegister (GPIO0 to 31)
union GPADAT_REG GPAPUD; // GPIO A Pull Up DisableRegister (GPIO0 to 31)
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B ControlRegister (GPIO32 to 63)
union GPB1_REG GPBQSEL1; // GPIO B QualifierSelect 1 Register (GPIO32 to 47)
union GPB2_REG GPBQSEL2; // GPIO B QualifierSelect 2 Register (GPIO48 to 63)
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register(GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register(GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B DirectionRegister (GPIO32 to 63)
union GPBDAT_REG GPBPUD; // GPIO B Pull Up DisableRegister (GPIO32 to 63)
Uint16 rsvd2 [8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register(GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register(GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C DirectionRegister (GPIO64 to 95)
union GPCDAT_REG GPCPUD; // GPIO C Pull Up DisableRegister (GPIO64 to 95)
};
Following EALLOW protected register (below this register is selected the external interrupt sources, with which port, the port number assigned to it can be put)
A register is 16 bits, and a group of the IO port 32, so some register has two.
Three, GPIO register declaration TI library file
below is a structure TI library file declaration:
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A ControlRegister (GPIO0 to 31)
union GPA1_REG GPAQSEL1; // GPIO A QualifierSelect 1 Register (GPIO0 to 15)
union GPA2_REG GPAQSEL2; // GPIO A QualifierSelect 2 Register (GPIO16 to 31)
union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register(GPIO0 to 15)
union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register(GPIO16 to 31)
union GPADAT_REG GPADIR; // GPIO A DirectionRegister (GPIO0 to 31)
union GPADAT_REG GPAPUD; // GPIO A Pull Up DisableRegister (GPIO0 to 31)
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B ControlRegister (GPIO32 to 63)
union GPB1_REG GPBQSEL1; // GPIO B QualifierSelect 1 Register (GPIO32 to 47)
union GPB2_REG GPBQSEL2; // GPIO B QualifierSelect 2 Register (GPIO48 to 63)
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register(GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register(GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B DirectionRegister (GPIO32 to 63)
union GPBDAT_REG GPBPUD; // GPIO B Pull Up DisableRegister (GPIO32 to 63)
Uint16 rsvd2 [8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register(GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register(GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C DirectionRegister (GPIO64 to 95)
union GPCDAT_REG GPCPUD; // GPIO C Pull Up DisableRegister (GPIO64 to 95)
};
The above-described structure is defined GPIO registers can operate directly, external pin initialization operation is completed. For example, the GPIO function IOA all settings, output state, quantization 0:
void Gpio_Select(void)
{Uint16 var1;
Uint16 var2;
Uint16 var3;
var1 = 0x0000;
var2=0xffff;
var3=0x0000;
EALLOW;
GpioCtrlRegs.GPAMUX1=var1;//GPIO0-15
GpioCtrlRegs.GPAMUX2=var1;//GPIO16-31
GpioCtrlRegs.GPADIR.all=var2;//GPIO0-31
GpioCtrlRegs.GPAQSEL1.all=var3;
GpioCtrlRegs.GPAQSEL2.all=var3;
EDIS;
}
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
union GPADAT_REG GPASET; // GPIO Data Set Register(GPIO0 to 31)
union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31)
union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31)
union GPBDAT_REG GPBDAT; // GPIO Data Register(GPIO32 to 63)
union GPBDAT_REG GPBSET; // GPIO Data Set Register(GPIO32 to 63)
union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63)
union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63)
union GPCDAT_REG GPCDAT; // GPIO Data Register(GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO Data Set Register(GPIO64 to 95)
union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95)
union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95)
Uint16 rsvd1[8];
};
Type register of each group is the same as stated above, but the location in memory is not the same. As the name suggests the reason is that the TI These registers are used as data registers.
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL;// XINT1 GPIO InputSelection
union GPIOXINT_REG GPIOXINT2SEL;// XINT2 GPIO InputSelection
union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection
union GPIOXINT_REG GPIOXINT3SEL;// XINT3 GPIO InputSelection
union GPIOXINT_REG GPIOXINT4SEL;// XINT4 GPIO InputSelection
union GPIOXINT_REG GPIOXINT5SEL;// XINT5 GPIO InputSelection
union GPIOXINT_REG GPIOXINT6SEL;// XINT6 GPIO InputSelection
union GPIOXINT_REG GPIOXINT7SEL;// XINT7 GPIO InputSelection
union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select
}
externvolatilestruct GPIO_CTRL_REGSGpioCtrlRegs;
externvolatilestruct GPIO_DATA_REGS GpioDataRegs;
externvolatilestruct GPIO_INT_REGS GpioIntRegs;
Using three variables corresponding to the structure as defined above to configure the GPIO port. (Elements of structures in the body is above the joint, see joint elements can be seen, the overall assignment register can also be assigned to one bit. As for value given what you need to view the data sheet or comments to see what features you want.)
Four, the GPIO configuration instructions
want to light a LED lamp, first look at the hardware schematics, to know the LED on the GPIO2, requires a low lighting. So we know to configure GPIO2 to general purpose IO, output, initialization time may turn off the LED, so the need to write a set (also see the above structure which elements the setting register, that is, to the corresponding elements assignment)
The EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // for doing pullup ON the Enable the GPIO2
(users have explained, when generally used as an output port, will pull provided, the purpose is to enhance the driving capability, while the input port does not matter)
GpioDataRegs. =. 1 GPASET.bit.GPIO2; // the Load Output LATCH
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; // = the GPIO2 the GPIO
GpioCtrlRegs.GPADIR.bit.GPIO2 =. 1; // Output the GPIO2 =
EDIS;
then, to the corresponding write command data register corresponding to the operation GPIO output values.
#define LED_OFF GpioDataRegs.GPASET.bit.GPIO2 = 1; // Close led, that is, writing to set the register GPIO2 1.
GpioDataRegs.GPASET.bit.GPIO2 in GpioDataRegs that is to say that the above-defined variables, and configuration elements GpioDataRegs, you need that element of union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31), then open this Commonwealth,
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
That is to configure this, continue to open,
2 port is needed, to put it a value of 1. (If the other port belonging to the groups of look is then replaced GpioDataRegs.GPASET.bit.GPIO2 of A, port 2 can be replaced required)
Such memories can: All GPIO port data registers have a common name GpioDataRegs, whose elements are the Commonwealth, the reason can be defined as the union of all the configuration, you can also configure a bit. Port A is set GPASET register (an element .bit GpioDataRegs is only one configuration, the element is .GPIO2 GPASET port 2 as bit elements.)
Fifth, the external interrupt configuration
F28335 the GPIO a total of 88, is divided into group 3, are A, B, C. Wherein group A GPIO configured by software as well as an external interrupt NMI function 2, Group B GPIO configured through software to function 3,4,5,6,7 external interrupt. The GPIO Group C can not be configured as an interrupt function. If a GPIO configured as an external interrupt function, then the next step is to set:
1. The digital I / O configuration as GPIO function;
2. The digital I / O configuration to the input direction;
3. The digital I / O configuration is correct quantization;
4. Select the external interrupt pin register selects the appropriate source for the external interrupt;
5. For this purpose GPIO trigger signal polarity setting, rising, falling, or both edges;
GpioIntRegs to configure an external interrupt when the selected interrupt sources. E.g:
GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 15; // put GPIO15 as an external interrupt source 1.
Peripheral to be able to successfully generate an interrupt response, it is necessary first of all by the peripheral interrupt enable level, and then by PIE allowed, then allowed by the CPU, the CPU makes a final response.
F28335 no external interrupt fixed interfaces, wherein GPIO0-GPIO31 may be configured as an external interrupt XINT1, XINT2 and NMI, wherein NMI attention from PIE management, and may be configured to XINT3 GPIO32-63 to XINT7.
If PIE interrupt management module, but also to configure PIE module, first outlined the principles of PIE:
On the map (INTX refers 1-12) except that a set of instructions. Now the block corresponding to the register. PIE interrupts within the module corresponding interrupt flag bit (the PIEIFRx) and an enable bit (PIEIERx.y) each. In addition, each interrupt PIE (INT1 ~ INT12) in response to a flag (PIEACK).
As shown in FIG: PIE whole management interrupt process is divided into 3, at the peripheral level, PIE stage, the CPU level (when a write interrupt control to write each part)
Entire interrupt process shown above:
(1) Peripheral level
when a peripheral interrupt, the interrupt event associated interrupt flag (IF) is set. At this time, if the interrupt corresponding to the interrupt enable register (IE) is also set to 1, the peripheral will send an interrupt request to the controller PIE. If the peripheral level interrupt is not enabled (the corresponding enable bit is 0), then it will not peripheral issues an interrupt request to the PIE, the corresponding interrupt flag will always remain set until cleared by software. Of course, interrupt flags remain at time 1, once the interrupt is enabled, the peripheral issues an interrupt will immediately apply to the PIE.
Note: In any case, the peripheral register interrupt flag must be cleared in software.
Summary:
peripheral interrupt mask needs to be registered in the interrupt enable 0 with the associated peripheral interrupt; (note 1 configuration enabled)
peripheral interrupt flag is cleared, it is necessary to interrupt associated with the outer set in the interrupt flag register 1;
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; // GPIO15 = GPIO
GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; // GPIO15 = intput
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 2; // XINT2 Qual using 6 samples
GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0x80; // Each sampling window is 128*SYSCLKOUT
GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 15;
EDIS;
// Configure XINT1
XIntruptRegs.XINT1CR.bit.POLARITY = 1; // Falling edge interrupt
// Enable XINT1
XIntruptRegs.XINT1CR.bit.ENABLE = 1; // Enable Xint1
In short, the peripheral interrupt configuration must be enabled peripheral interrupt peripheral interrupt flag is cleared, the corresponding peripheral configuration (such as an external interrupt port to configure the IO, IO configured as input, rising or falling edge interrupt and other specific configuration you can view the register description)
(2) PIE stage
when the peripheral interrupt events associated interrupt flag bit, interrupt enable bit is enabled, the peripheral interrupt request will be submitted to us PIE module . PIE module 96 and an outer peripheral pin interrupt packet, divided into 12 groups of eight interrupts, are PIE1-PIE12. Interrupt is pooled for each group of multiplexers enter a CPU interrupt, e.g. PDPINDA, PDPINDB, XINT1, XINT2, ADCINT, TINT0, WAKEINT seven interrupts are within PIE1 group, which are brought together to interrupt CPU interrupt INT1.
Summary:
PIE interrupt enable. Must be enabled for the respective groups of which the bit is set to PIEIERx;
the PIE interrupt masking. This is to enable the inverse operation and;
the PIE response PIEACK clear register bit related to the interrupt so that the CPU can respond to the same group of the other.
Compare interrupt interrupts and peripherals grade PIE class: peripheral interrupt pending bit software is required to clear the interrupt flag PIE level are automatically set or cleared. But more than a PIEACK PIE register, at the same time can only put a break in the past, only to wait until this interrupt is set to PIEACK, under the same group to make a break in the past, acknowledged CPU, while the response time after the interruption when PIEACK will automatically set, it is necessary to write software 1 cleared
PIE96 corresponding interrupt peripherals as follows:
Corresponding interrupt has a corresponding position in PIE, such as external interrupt 2 in INT1.5.
PIE-level software programming:
// Initialize the PIEcontrol registers to their default state.
// The default state isall PIE interrupts disabled and flags
// are cleared.
InitPieCtrl (); // initialize PIE, were closed and cleared up
After PIE register operation, must first register enable PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;// Enable the PIE block
There are clear response register. The following can be used directly
// Enable CPU and PIE interrupts
// This example function is found in the DSP2833x_PieCtrl.c file.
EnableInterrupts();
PIE and enables the corresponding interrupt enable register, i.e. the following code
PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Gropu1 INT4 correspond to the peripheral interrupt vector table to XINT1
(UP table understood XINT1 i.e. external interrupt 1 is located in the first group of the fourth, i.e. PIEIER1 and INTx4, energy corresponding to the interrupt enable)
Then make sure the corresponding interrupt service routine is mapped to the interrupt vector table
EALLOW; // This is needed to write to EALLOW protectedregisters
PieVectTable.XINT1 = &xint1_isr;
EDIS; // This is needed to disable write to EALLOWprotected registers
Finally, it must correspond to Group1 is in the interrupt service routine PIEACKx = 1 write 1 cleared
(. 3) Level CPU
CPU flag register IFR and also enable register IER. When a peripheral interrupt request to the CPU via the PIE, CPU level associated with the INTx interrupt flag bit is set. For example, the period Tl arrives CPU interrupt request T1PINT side, INT2 associated flag will be set. At this time, the flag will be present in the IFR, this time, the CPU not to execute the corresponding interrupt immediately, but waits CPU can make the relevant bit register IER, and the CPU register ST1 in the global interrupt mask bit make the appropriate enabled. If the IER the associated bit is set, and the INTM is 0, then the CPU will be interrupted in response. In T1PINT, the second position when the IER i.e. INT2 is set, INTM is 0, the CPU will interrupt response timer period T1. CPU received a request from the terminal, you have to suspend the program being executed and instead to respond to an interrupt routine, but this time, it had to do some preparatory work, in order to perform'll find back to its original place after the completion of the interrupt routine and the original state. CPU will IER and the corresponding IFR bit is cleared, EALLOW also cleared, INTM is set, they can not respond to other interrupts, CPU interrupts issued a notice to the other, being busy, no time to process your request, and have to after processing until the interrupt hands before handling your request again. After then, CPU execution and memory automatically saved return address information, such as data on the stack being processed, etc., make these preparations, CPU execution interrupt vector corresponding ISR removed from PIE block to turn to the implementation interrupt subroutine.
CPU interrupt level summary:
CPU-level operations are automatic, either interrupt flag (IFR), or interrupt enable bit (IER).
But can the opening break through software settings, disable interrupts. (And the configuration will turn off before the break interrupt, clear the flag bit)
// Disable CPU interrupts
DINT;
/ Disable CPU interruptsand clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
12 28335 Large group interrupted by an interrupt register IER core CPU to control, i.e. to determine IER in the end belongs to which group each interrupt Interrupt large (e.g., control of the PIE IER | = M_INT12;. We use the description of the interrupt 12, but the first group What 12 groups inside interrupt the CPU does not know that this would need to be determined by PIEIER. among them, each group has its own PIEIER register.)
The CPU IFR register is the interrupt group (ie, the 12 group) of the flag register.
IER | = M_INT12; // Enable CPU corresponding interrupt enable register, the CPU INT12 interrupt is enabled.
/ Enable globalInterrupts and higher priority real-time debug events:
EINT; //Enable Global interrupt INTM
ERTM; //Enable Global realtime interrupt DBGM
When the external interrupt software written :( set to shut off the main and interrupt flags, and finally open)
Configure the port GPIO ports for input.
GpioIntRegs then configure the GPIO port select register GPIOXINTnSEL (also immediate interrupt source), e.g. GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 0; // Xint1 is GPIO0
Then configure XIntruptRegs in XINTnCR to configure some parameters interrupt (trigger mode, enabling interrupts, etc.): For example:
// Configure XINT1
XIntruptRegs.XINT1CR.bit.POLARITY = 0;// Falling edge interrupt
// Enable XINT1
XIntruptRegs.XINT1CR.bit.ENABLE = 1;// Enable Xint1
Wherein XINTnCTR count register is to be used, the configuration may not be
Other peripherals overall process is as follows :( set the time to shut off the main and interrupt flag)
Sixth, the code sample
// Step 1. Initialize SystemControl:
// PLL, WatchDog, enablePeripheral Clocks
// This example functionis found in the DSP2833x_SysCtrl.c file.
InitSysCtrl (); // watchdog off, setting the clock 150MHZ, note clock corresponding peripheral opening.
// Step 2. Initalize GPIO:
// This example functionis found in the DSP2833x_Gpio.c file and
// illustrates how to setthe GPIO to it's default state.
// InitGpio(); // Skipped for this example
Led_Gpio_Init (); (this is according to their own needs write the configuration GPIO function)
// Step 3. Clear all interrupts andinitialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIEcontrol registers to their default state.
// The default state isall PIE interrupts disabled and flags
// are cleared.
// This function is foundin the DSP2833x_PieCtrl.c file.
InitPieCtrl (); // initialize PIE, were closed and cleared up
// Disable CPU interruptsand clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIEvector table with pointers to the shell Interrupt
// Service Routines(ISR).
// This will populate theentire table, even if the interrupt
// is not used in thisexample. This is useful for debugpurposes.
// The shell ISR routinesare found in DSP2833x_DefaultIsr.c.
// This function is foundin DSP2833x_PieVect.c.
InitPieVectTable (); // initialize the interrupt vector table
// Interrupts that areused in this example are re-mapped to
// ISR functions foundwithin this file.
EALLOW; //This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_xint_isr;
(DSP2833x_PieVect.h can be found in the header file declare the structure to see to know the elements PINT TINT0; // Timer 0, the address of the interrupt function that can be assigned to write)
EDIS; //This is needed to disable write to EALLOW protected registers
// Step 4. Initialize the DevicePeripheral. This function can be
// found in DSP2833x_CpuTimers.c
InitCpuTimers(); // For thisexample, only initialize the Cpu Timers
ConfigCpuTimer (& CpuTimer0,150, 50); (just configure Timer 0, as this is written, the timer 0 interrupt)
// To ensure precisetiming, use write-only instructions to write to the entire register. Therefore,if any of the configurationbits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h),the below settings mustalso be updated.
// CpuTimer0Regs.TCR.all = 0x4001; // Usewrite-only instruction to set TSS bit = 0
// CpuTimer1Regs.TCR.all = 0x4001; // Usewrite-only instruction to set TSS bit = 0
// CpuTimer2Regs.TCR.all = 0x4001; // Usewrite-only instruction to set TSS bit = 0
// Step 5. User specific code,enable interrupts:
// Enable CPU int1 whichis connected to CPU-Timer 0, CPU int13
// which is connected toCPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER | = M_INT1;
(#Define M_INT1 0x0001 in DSP2833x_Device.h in)
(Since only uses the timer 0, so only open the corresponding CPU Timer 0 Interrupt Enable Register)
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
Seems clear response should be added to the register of the PIE.
// Enable TINT0 in thePIE: Group 1 interrupt 7
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
(Open the interrupt timer 0 in the corresponding enable register PIE)
// Enable globalInterrupts and higher priority real-time debug events:
EINT; //Enable Global interrupt INTM
ERTM; //Enable Global realtime interrupt DBGM
After the can.
#include "DSP2833x_XIntrupt.h" // External Interrupts
When configuring external interrupt to use this header file. DSP2833x Device External Interrupt Register Definitions.
