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Correct choice of MOS transistor is a very important aspect, not select MOS transistor may affect the efficiency and cost of the overall circuit, the nuances of the different parts and different MOS transistor switching circuit allows engineers to avoid the stress problems. Let's learn the correct method of selection MOS transistor under.
The first step : selection of a P-channel or N-channel for the first step in designing the device is determined to select the correct N-channel or P-channel MOS transistor. In a typical application of power, when a MOS transistor is grounded, and the load connected to the mains voltage, the MOS transistor constitute a low-side switch. In the low-side switch, it will be an N-channel MOS transistor, which voltage is out of consideration of the desired device is turned on or off. When the MOS transistor is connected to the ground bus and the load necessary to use high-side switch. Usually employed in the P-channel MOS pipe topology, which is out of consideration for voltage driving. To select a device suitable for the application, the voltage required to drive the device, and a method performed in the most simple design must be determined. The next step is the maximum rated voltage to determine the required, or the device can withstand. The larger the rated voltage, the higher the cost of the device. According to practical experience, the rated voltage should be greater than the mains voltage, or bus voltage. So as to provide adequate protection, the MOS pipe will not fail. To select MOS transistor, it must determine the maximum voltage between the drain-to-source may be subjected, i.e. the maximum the VDS. Know MOS transistor can withstand the maximum voltage that varies with temperature This is important. Designers must test voltage range over the entire operating temperature range. Rated voltage must have sufficient margin to cover this variation range, ensure that the circuit will not fail. Other safety factors designers need to consider the electronic device comprises a switch (such as a motor or a transformer) induces a voltage transients. Rated voltages of different applications are different; typically, the portable device is 20V, FPGA power of 20 ~ 30V, 85 ~ 220VAC application is 450 ~ 600V.
The second step : The second step is to determine the rated current of the MOS transistor current rating. Depending on the circuit configuration may be that the maximum current rating should be able to withstand the current load in all cases. Similar to the case of the voltage, the designer must ensure that the selected MOS transistor can withstand the rated current, even when the peak current is generated in the system. Consider the case of two current continuous mode and spikes. In continuous conduction mode, the MOS tube is in a steady state, when the current through the device continuously. Refers to a large number of spikes surges (or peak current) flow through the device. Once the maximum current under these conditions, only the direct selection devices can be able to withstand the maximum current. After selecting the rated current, but also the conduction loss must be calculated. In practice, the MOS tube is not an ideal device, since there is power loss in the conductive process, which is called conduction losses. MOS transistor in the "on" as a variable resistor RDS is determined by means of (the ON), and vary significantly with temperature. Power dissipation of the device can be Iload2 × RDS (ON) is calculated, since the on-resistance varies with temperature, so the power consumption will also vary in proportion. The higher the voltage VGS of the MOS transistor is applied, RDS (ON) will be smaller; otherwise RDS (ON) will be higher. For system designers, this is dependent on the system voltage and the need to weigh the trade-off place. Portable designs, a lower voltage is easier (more common), and for industrial design, a higher voltage may be employed. Note RDS (ON) resistance may rise slightly as the current.Various electrical parameters on RDS (ON) resistance can be found in the technical data sheet provided by the manufacturer. Technology has a major influence on the characteristics of the device, because some technologies tend to make RDS (ON) increases when increasing the maximum VDS. For such technique, if the VDS and going to lower RDS (ON), it would have increased the size of the wafer, thereby increasing the package size and the ancillary related development costs. Existing attempts to control the industry are several techniques to increase the size of the wafer, which is the main channel and electric charge balance techniques. The channel technique, a wafer is embedded deep, usually reserved for low voltage, for reducing the on resistance RDS (ON). To reduce the impact on the maximum VDS RDS (ON), the development of the epitaxial growth process used in the column / column etching process. For example, a Fairchild developed the technique known as SupeRFET for reducing RDS (ON) increases the additional manufacturing steps. This kind of RDS (ON) of interest is important because when the standard MOSFET breakdown voltage is increased, RDS (ON) will follow increases exponentially, and causes the wafer size is increased. The process SuperFET exponential relationship between the RDS (ON) and becomes a linear relationship between the size of the wafer. Under such, the device can be in the SuperFET small die size, and even the breakdown voltage reaches 600V, the ideal low RDS (ON). The result is a wafer size can be reduced 35%. For the end user, which means that significantly reduced package size.
The third step: determining the heat required to select the next MOS transistor is cooling requirements of the computing system. Designers must consider two different cases, that is the worst case and the real situation. The results suggested for the worst case, because the results provide a greater margin of safety, to ensure that the system will not fail. There are to be noted in the measurement data table MOS transistor; such as thermal resistance between the semiconductor junction and the environment of the packaged device, and the maximum junction temperature.
器件的结温等于最大环境温度加上热阻与功率耗散的乘积（结温=最大环境温度+[热阻×功率耗散]）。根据这个方程可解出系统的最大功率耗散，即按定义相等于I2×RDS（ON）。由于设计人员已确定将要通过器件的最大电流，因此可以计算出 不同温度下的RDS（ON）。值得注意的是，在处理简单热模型时，设计人员还必须考虑半导体结/器件外壳及外壳/环境的热容量；即要求印刷电路板和封装不会立即升温。
雪崩击穿是指半导体器件上的反向电压超过最大值，并形成强电场使器件内电流增加。该电流将耗散功率，使器件的温度升高，而且有可能损坏器件。半导体公司都会对器件进行雪崩测试，计算其雪崩电压，或对器件的稳健性进行测试。计算额定雪崩电压有两种方法；一是统计法，另一是热计算。而热计算因为较为实用而得到广泛采用。除计算外，技术对雪崩效应也有很大影响。例如，晶片尺寸的增加会提高抗雪崩能力，最终提高器件的稳健性。对最终用户而言，这意味着要在系统中采用更大的封装件。
第四步：决定开关性能 选择MOS管的最后一步是决定MOS管的开关性能。影响开关性能的参数有很多，但最重要的是栅极/漏极、栅极/ 源极及漏极/源极电容。这些电容会在器件中产生开关损耗，因为在每次开关时都要对它们充电。MOS管的开关速度因此被降低，器件效率也下降。为计算开关过程中器件的总损耗，设计人员必须计算开通过程中的损耗（Eon）和关闭过程中的损耗（Eoff）。MOSFET开关的总功率可用如下方程表达：Psw=（Eon+Eoff）×开关频率。而栅极电荷（Qgd）对开关性能的影响最大。
