I / O devices is an important part of the computer, ranging from the complexity of the processor I / O devices to interact with, and I / O operation has been a technical point of high-level language developers more difficult to grasp.
Because the high-level language package for I / O operating system functions based operating system, which is called by these systems function and its structure and working mechanism of the hardware layer of closely related, so those who want to completely get to know the function I / O operations, you must have some understanding of their work based on the underlying device. Here we look at the process I / O operations evolution.
Polling mode I / O operation
Program I / O device polled mode, a computer system is the early management of I / O devices. It is the timing of various devices in turn asks again whether or processing requirements. After asking in turn, has required, then it is addressed. After the process of claim I / O device, the processor returns to continue working. While polling takes time, but the speed than the polling I / O devices is much faster, the problem does not occur normally can not handle, timeliness I / O operation is guaranteed. However, even faster processor, the number of input and output devices are also capable of handling a certain limit. Further, the program takes up a considerable portion of the polling CPU processing time, thus polling procedure is a less efficient way, in modern computer systems rarely used.
2. interrupt the I / O operation
Between processors and I / O devices several orders of magnitude difference in speed is an important contradiction I / O operations exist, device management is an important issue to be solved. To increase overall efficiency, to reduce the direct control of a program I / O devices to interact with the data processor is necessary. In the I / O device interrupt, the step of transmitting data between the central processor and the I / O device are as follows:
⑴ when a process requires data, issued a directive to start preparing the data input and output devices
⑵ issues an instruction after starting the process equipment, the process give up the processor, the process by the operating system to set a blocked state, waiting for the relevant I / O operation is completed. At this point, the process scheduler will schedule other processes that use processor-ready.
⑶ When the I / O operation is completed, the input-output device controller issues an interrupt request line by an interrupt signal to the processor, the processor after receiving an interrupt signal, the steering predesigned interrupt handler, the data transfer process corresponding work .
After ⑷ data ready, OS will block the process wakes up, it was taken into the ready state. At some subsequent time, the process scheduler will select the process continues to work.
The advantages and disadvantages of interrupt
Utilization of I / O device interrupt causes the processor to improve, and can support multi-channel parallel operation program and I / O devices.
However, there are still some problems interrupt. First of all, modern computer systems are typically configured with a variety of input and output devices. If the I / O devices with interrupt handling through parallel operation, the interrupt will cause a sharp increase in the number of CPU can not respond to interrupt and data loss phenomenon.
Second, if the data buffer I / O controller is relatively small, it will interrupt occurs after the buffer is full of data. Then, in the data transfer process, the more chance interrupt occurs, it will burn off a lot of CPU processing time.
In order to distinguish here at An I / O mode, we talk about the work I / O devices. We start to understand a hardware device, the device controller.
2.1 Device Controller
The controller entity is a computer device in its main functions are to control one or more I / O devices, to enable data exchange between the I / O devices and the computer. It is the interface between the CPU and the I / O device, it receives a command sent from the CPU, and to control I / O devices work, so that the processor freed from the complex device control transaction. The controller device is an addressable device, it is only when a control device, which is only a unique device address; If the control can be connected to a plurality of devices, comprising a plurality of devices should address and each device address corresponds to a device. Device controller has many responsibilities, we just say that this explanation related to the duties of that data exchange.
Data exchange means for data exchange between the controller and the device between the CPU and the controller. For the former, through a data bus, the parallel data is written to the controller by a CPU, or data is read out in parallel from the controller; the latter, the data is input to the controller device, or from the controller to the device . For this reason, the data shall be provided in the controller register.
We mentioned above, the interrupt controller device is issued to the processor, it is conceivable data exchange process:
1. 100M processor needs data on the disk, and then issues a read command to the disk processor, and process to block until the data is ready.
2. The disk processor receives the read instruction, a seek / addressing and other data to find the target disk operations, the read data to the disk processor registers. Assuming that Memory capacity is 1M, after waiting for an interrupt to the CPU register read full.
3. CPU receives an interrupt signal, wake-up process data read instruction, reading data from the disk controller to the memory register. Waiting to read is complete, no data can be read, continue to enter the blocked state.
4. The disk controller to read the data again to the disk register is 1M, once again send an interrupt to the CPU. Cycle, until the 10 M data read completion.
It can be seen optimize the overall idea is that by interrupting mechanism, the device controller reads the data from the device to register to save time out, CPU will not wait on this busy time, you can do other meaningful things . Not to mention, this idea is very similar to the lock to achieve, it is to optimize non-peak busy wait wait, avoiding ineffective operation of the CPU.
But just under the drawback is also very clear about the frequent interruptions will increase the pressure on the CPU, in particular register some of the equipment controller is relatively small, the operation of the interrupt frequency is very high once I / O. Also the data read from the kernel buffer to the device processor is the whole process of CPU intervention, byte by byte read or write to these operations and there is no complex logic, it is directly processed by the CPU and some waste of resources.
3. DMA mode I / O operation
Direct Memory Access means, into the data block transfer directly between memory and I / O devices. This technique is based DMA device, a CPU freed from simple data transmission job.
There are two features of DMA, direct transfer first, followed by a block. The so-called direct transfer process, i.e., a data block transfer between the memory and the IO device, any intermediate without CPU intervention, only CPU issues a command "transport block data" to the device at the beginning of the process, and then be learned by the interrupt whether the process is complete and ready for the next operation is, of course, this is not the interruption device controller DMA device sent to the CPU.
DMA working process:
When ⑴ When the process equipment required input data, CPU for storing the input data to prepare the memory starting address and the number of bytes to be transferred are sent to the DMA controller in the memory address and the transfer byte counter register.
⑵ issued requirements for data transmission enters a waiting state. CPU instruction is being executed at this time is temporarily suspended, the process enters the blocked state. Process scheduler scheduling other processes occupy the CPU.
⑶ input device constantly steal CPU cycles work (or for the CPU memory bus), the data buffer register into memory steady flow until the required bytes will be transferred.
⑷DMA controller, when all bytes been transferred, an interrupt request line by an interrupt signal is issued. After the CPU receives the interrupt signal, the interrupt processing routine proceeds to subsequent processing.
After ⑸ interrupt processing, CPU returns to the interrupted process, or switch to a new process contexts, continue.
DMA and interrupt the difference
⑴ interrupt is issued after the device controller data buffer register full interrupt issued by the device controller, the CPU interrupt processing required, and the DMA mode is in the data block transfer request interrupt process all the requirements of the CPU at the end of the transfer , issued by the DMA device. This greatly reduces the number of CPU interrupt processing.
⑵ data transfer mode is interrupted when the interrupt processing is completed by the CPU of the control, while the DMA mode is under control of the DMA controller, without CPU control is completed. This eliminates the CPU due to parallel processing, and too many devices and too late because they do not match the speed of data loss and so on.
Advantages and disadvantages of the DMA
In the DMA mode, since the I / O device to block the data exchange occurs directly with memory, I / O is more efficient. Since DMA technology can improve I / O efficiency, so the modern computer systems, it has been widely used. Many O device controllers, device controller block in particular, support DMA mode.
Can be seen from the above analysis, the strength of the DMA controller function, a key factor in determining the efficiency of DMA. DMA controller for each data transfer requires a lot of work, reducing the mean number of transmissions increases data transfer unit. Further, the DMA clock cycle steal mode, because it occupies a memory data bus access, the processing efficiency of the CPU is reduced, in order to minimize the cycle steal always, will try to improve the performance of the DMA controller, which may be less influence CPU processing efficiency.
DMA is generally a relatively satisfactory approach, DMA device by introducing the CPU from the heavy freed I / O operations. CPU only needs to send a read request and obtaining processing results, without the need to focus on the specific transmission process I / O operations.
4. The embodiment of the channel I / O
Input / output channel is independent of the CPU a dedicated management of I / O processor, which controls the memory device and to exchange data directly. It has its own command channel, the channels initiated by the CPU instructions, and issue an interrupt signal to the CPU at the end of the operation. The input / output control channel is a kind of memory as the center, to achieve direct exchange devices and memory control data. In the channel, the direction of data transfer, data storage memory starting address and block length of data transmitted by the channel and the like to control. Further, the channel control can be done a plurality of control channel to exchange data with the memory device. Thus, the channel mode to further reduce the burden on the CPU, increasing the degree of parallel working computer system.
In different types of information exchange and the connected device, channels can be divided into the following three types:
⑴ byte multiplexor
It is suitable for connecting a low-speed or medium-speed printers, terminals and other I / O devices. Such a channel cross bytes work: when the device transmits a byte is one, is immediately transferred to a byte transfer it to another device.
⑵ select the channel
It is suitable for connecting disk, tape, and other high-speed devices. This channel to "burst mode", and each group of data transfer, the transfer rate is high, but over a period of time can only be one device services. Whenever an I / O request after processing, and selects its services to another device.
⑶ group multiplexor
This channel combines the byte multiplexor select a high time-sharing, and the transmission rate characteristics of the channel, its essence is: multi-channel programming techniques the channel program, so that the device can work with the channel connected in parallel.
In the control channel mode, I / O device controller (often referred to as I / O controller) are not transmitted byte counter, and a memory address register, but a multi-channel device controller and the instruction execution section. CPU simply issue start command indicating respective operation channels and I / O devices, this instruction can be started and the channel of the channel up channel corresponding instruction from memory for execution. Once the CPU issues an instruction to start the channel, the channel began to work. I / O channel control I / O controller work, I / O controller and the control I / O devices. In this way, a channel may be connected to a plurality of I / O controller and one I / O controller and a number of units of the same type can be connected to an external device. Since the number of channels and the controller is typically less than the number of devices, and therefore, if improperly connected, often resulting in a "bottleneck." It is connected to cross-connect equipment in general use, benefits of doing so are:
① improve the reliability of the system: When a pathway or channel failure by the controller is disconnected, may use other paths.
② improve the parallelism of the device: a device for the same, when a certain passage in the controller connected to it or the channel is occupied, can select another free channel, the device reduces the time spent waiting for the required passage.
Channel processor
Corresponds to a simple function of channel processors, it has its own instruction set, including read, write, control transfers to end operation instruction and air, and may be written by executing the channel program instructions.
Arithmetic control channel means comprises:
① channel address word (CAW): the recording address of the next instruction stored in the channel, which functions similarly to the central processor instruction register.
② channel command word (CCW): channel recording instruction is being executed, which acts as a central processor instruction register.
③ channel status word (CSW): recording status of the channel, the controller, the apparatus including I / O transfer completion information, error messages, number of times repeatedly performed.
Generally we need to share the same channel and the host memory, to save the program and switching the channel data. Memory access channel using "cycle stealing" mode. With passage way, the process input / output is as follows:
CPU encounters I / O request when the user program is executed based on the user's I / O request generates a channel program (which may be pre-programmed). Into memory, and the first address of the channel program into the CAW.
Then, the CPU performs "Start I / O" command, to start working channel. Channel receiver "Start I / O" signal command, the first address of the channel program taken from the CAW and the first instruction is fetched channel program according to this address into the CCW; simultaneously to send reply signal CU, the notification "Start I / O "instruction completion is completed, CPU can continue.
Channel starts executing the channel program, the physical I / O operations. When executing the instruction after, if there is the next instruction execution continues; otherwise, it indicates the completion of transmission, while the stop on their own, notify the CPU to process the end of the transfer channel event, and with the relevant channel status from the CCW. In short, in the channel, I / O using an auxiliary processor dedicated I / O operations, thereby reducing the processing load of the host processor I / O's. As long as the host processor issues an I / O operation command, the remaining work entirely by the channel. After the I / O operation, I / O channels will issue an interrupt request, it indicates that the corresponding operation is complete.
The idea is to develop from the early passage of large-scale computer systems together. In the early mainframe computer system, the general Peiyoutailiang I / O devices. In order to manage the I / O devices are separated from the host computer, the concept of forming I / O channels, and a specially designed I / O channel processor. I / O channel is a very important component in the computer system, improve the overall performance of the system it plays a very important role. However, with the development of technology, to continuously improve the processor and I / O device performance, dedicated, independent I / O channel processor is not easy to see. But the idea of channels and incorporates many new technologies, it is still widely used with. Since the optical fiber having data transmission channel technology
A high transmission rate, the data transmission distance and advantages of simplified design mass storage systems, new common Fiber Channel technology is rapidly developing. This general fiber channel 127 can accommodate up to a large-capacity hard drives on one channel. Obviously, a high-speed large-capacity storage applications, Universal Fiber Channel has a wide range of applications.
For the first three I / O interaction, the following features:
1. requires CPU intervention: polling require full CPU intervention; interrupt mode requires CPU intervention entirely, but the CPU non-busy waits in the meantime, you can do other things; DMA transfer mode requires CPU in the beginning and the end of the intervention.
2. Need hardware support: poll requires only the most basic processor can; the need to increase the interrupt mode interrupt controller; DMA DMA mode requires a processor and interrupt controller.
These three ways for peripherals are not too many minicomputers, for I / O multi-device input and output complex system, taking up too much CPU time, the hardware interface is too complex. Channel technology so that the CPU can manage a large number of external devices with limited I / O instructions, instead of the CPU peripheral control and management.
The device controller increases between the CPU and I / O devices can greatly reduce the interference has the CPU I / O, so that the CPU is freed from many io process, but when the outer configuration of the host device number, CPU load also very heavy, and for this purpose the addition of I / O channels between the CPU and the device manager whose main purpose is to establish an independent operation io, so that not only the transfer of data independent of the CPU, but also want to organize the relevant I / O device / management and the end of the process to be independent, it simply put, is to find one thing to have a simple data processing capability to share CPU tasks, so that the CPU dedicated to those advanced data processing, simple processing of these data is given to this thing is something to deal with this I / O channels, I / O channels belonging to the hardware, but the ability to perform simple instructions. DMA controller is similar hardware, but no dedicated DMA controller processor, although DMA peripherals and memory without CPU perform data exchange work, but this is only reduces the burden on the CPU. Thus DMA, the initialization input and output still to be done by the CPU.
Thing in common: the forward pass can achieve the establishment of a data path between the IO and memory devices;
difference:
- We can only achieve a fixed DMA data transfer control, and the channel has its own instructions and programs with independent ability to handle more data input and output.
- DMA control only one or a few units of similar devices, and a channel control multiple similar or different devices.