The basic concept of interruption
Usually referred to interrupt a program interruption, refers to the CPU during normal operation of the program, due to a variety of pre-arranged or random internal or external event occurs, the CPU interrupts the running program, and go to the appropriate server program to handle this process is called a program interruption.
Two, 80x86 80x86 microprocessor interrupts the microprocessor interrupt type generally divided into two types, i.e., due to the execution of certain software instructions and interruptions caused by a processor other than the control circuit issues an interrupt request signal hardware interrupt caused. From the main CPU to the interrupt service routine, you must know the interrupt service routine entry address of the interrupt vector. 80x86 CPU for the PC, a total of 256 interrupt vectors.
The general process interruption:
When only the main apparatus A, B, C data is ready to deal with it A, B, C, data exchange. When slower peripherals prepare their own data, CPU to perform their usual main program. In this sense, some of the operation of the CPU and peripheral devices are performed in parallel, the program query therefore be compared with the serial, the efficiency of the computer system is greatly improved. As shown below:
The actual interruption process even more complicated, a detailed flowchart illustrating the processing procedure of the interrupt. When the CPU after executing - Article current instruction, if an interrupt request to a peripheral CPU, the CPU response with satisfying the condition, an interrupt is issued in response to the signal, at the same time close the interrupt ( "interrupt mask" flip-flop "1 "), it means that the CPU will not accept another - interruption of devices. At this time, CPU will look interrupt request source which device. And save the contents of CPU its own program counter (Pc) of. It then transferred to process the interrupt source of the interrupt service routine. In the Save CPU information field device (e.g., text data exchange) after. The recovery site information. After the completion of these actions, open interrupt ( "interrupt mask 'flip-flop' o"), and returns to the next instruction of the original network is interrupted main program.
When (1) Although the external interrupt request is random, but the CPU only after a current instruction execution is completed, the operation is transferred to the public interrupt request accepting apparatus, so that the execution of the current instruction and avoid the interference. Refers to a well operation instruction executed after the operations performed by the CPU, such as interrupt handling, direct memory transfers, instructions and the like to remove. Source external interrupt request latch signal is typically stored in the interface's, and is connected to the CPU through an interrupt request line, every time an instruction is executed to the end, then check the CPU interrupt request signal. If the interrupt request signal is "1", the CPU goes to "break the cycle", accepting external interrupts. (2) In order to properly return to the original main routine is interrupted breakpoint (PC content) After the interrupt service routine is finished and continue with the main program, must state the contents of the program counter PC, and the current CPU instruction execution after the end of (including some of the contents of the register and status flags) are saved to the stack. The operation is called to save the scene. (3) When the CPU interrupt, the interrupt service routine to go positive, there may be another new interrupt source to an interrupt request it. In order not to cause confusion, there must be a trigger interrupt mask in the interrupt managing section of the CPU, it can be set to "1" (setting screen), or set to "0" (removing the shield) under program control. Only when the interrupt mask flag is "0", CPU can accept an interruption. When an instruction completes CPU accepts an interrupt request and in response, it issues an interrupt response signal INTA one hand, on the other hand the interrupt mask flag is set to "1", i.e. the interrupt disabled. Thus, CPU can not accept additional new interrupt sources to interrupt requests sent. Only after the CPU interrupt service routine is finished, it was re-enable interrupt mask flag to "0", that is open break, and return to the main program. Therefore, the interrupt service routine must have the last two instructions, which means interrupt instruction and return to the main command while in the hardware to ensure that only accept new interrupt request after the return of the main instruction is executed. (4) the process is interrupted by the hardware and software to complete. As in the previous figure, is implemented by hardware interruption period, the interrupt service routine implemented by a sequence of machine instructions. In addition to the save the latter site, site restoration, open break and returns to the routine tasks, requirements interruption of service equipment, so the exchange of data with the CPU of a word, or for other services.
The basic concept of polling
Polling (the Polling) I / O mode or programmed I / O mode, it is to allow the CPU to query a certain period in sequence each peripheral to see if it has a required input or output of data, and if so, the corresponding input / output service; without, or I / O processed Bo, then the CPU will query the next peripheral.
Hardware required: Peripheral interface provides status port, data port
Software mechanisms: application must query the timing status of each interface port, determines whether input and output data, if necessary, the data operation is performed through the data port.
Features: CPU initiative to query external devices by executing instructions, the external device in a passive position.
The picture above shows the general process.
Comparison of polling and interrupt mode
speed
Program control:
Hardware speed indicator: As the "control program" fully software embodiment for controlling the peripheral interface, so it is just an ordinary hardware port write operation, there is nothing special, and the speed indicator by the bus transmission rate, a port responsiveness joint decision.
For this peripheral control mode, speed is a key indicator software.
Interrupt handling:
Atomic operation interpretation and program control mode interrupt processing per se is made uniform.
Because only added to determine the entry address of the interrupt interrupt request and response mechanism, for reading the state of the port into a reading of the interrupt number in response to the interrupt process, the state of the port is determined to become.
In essence, the same speed interrupt handling their own indicators and control procedures, there is no big difference.
reliability
Program control:
Since the hardware does not support interrupt mode, so the operating system after the CPU control to the application, as long as the application does not return control of the CPU, the operating system has been unable to regain control of the CPU (no timer interrupt). Applications and operating systems are software modules, operating system is the core module, there is a relationship between the transfer of control of the CPU them. It is because of this relationship, once the use of peripherals "Program control" application deadlock, the operating system will never be able to regain control of the system. Application failures from affecting the operating system as the core module through the peripheral control mode, therefore, based on the calculated reliability index associated with known, low reliability index associated with "programmed mode".
Interrupt handling:
By providing timer interrupt, the operating system can regain control of the CPU through the interrupt service routine applications at the end of the current time slice. The failure of the application does not spread to the operating system, therefore, high reliability index associated with the interrupt handling.
Scalability
Program control:
Because all applications are included to the port, once designed a hardware interface changes, all applications must be modified, which would modify the cost of increased many times. Thus, program control will partially modified metrics related to hardware modules is relatively low.
Interrupt handling:
Application does not directly operate the port, to the port by the interrupt service routine to complete. If the design of a hardware interface has changed, only need to modify its associated interrupt service routine can be. Thus, the interrupt handling related hardware modules such modified locally higher index.
Lifetime
"Program control" (CPU query mode) in early computer systems to meet the application requirements; but with the proliferation of types of external devices, to increase the speed difference, this approach has become the obstacle to system performance improvement. Its lifetime is limited to the early stages of a computer, because there was little external device, and are low-speed device, to occur after the 8-bit machine, this peripheral control (architecture) is eliminated.
"Interrupt handler" (peripheral request mode) can coordinate the speed difference between the CPU and peripherals, to coordinate the speed differences between various peripherals, improve the efficiency of the system (speed indicator). Allows applications from the basic operation of the peripheral off, reducing equipment-related procedures (the associated reliability indicator, partial modification indicators). Although some fast devices communicate with each other not by CPU, it did not use interrupt handling, but for the slow processing equipment, equipment failure, the interrupt handling is still the most effective. Whether future computer system component changes in how, as long as the conflict between slow and fast CPU devices exist, the use of interrupt handling is suitable. Even without using the interrupt service routine, interrupt the concept will remain for a long time. In a short time, the computer system can not leave in all areas of human interaction, people of a certain operating speed is slower than the processing speed of the machine, so the device will still slow (but this is not the only reason for the existence of a slow device) remains present. Because there is such a demand, interrupt handling has a longer life span.
(Reprinted from: http: //www.cnblogs.com/jhxk/articles/1893314.html)
The basic concept of interruption
Usually referred to interrupt a program interruption, refers to the CPU during normal operation of the program, due to a variety of pre-arranged or random internal or external event occurs, the CPU interrupts the running program, and go to the appropriate server program to handle this process is called a program interruption.
Two, 80x86 80x86 microprocessor interrupts the microprocessor interrupt type generally divided into two types, i.e., due to the execution of certain software instructions and interruptions caused by a processor other than the control circuit issues an interrupt request signal hardware interrupt caused. From the main CPU to the interrupt service routine, you must know the interrupt service routine entry address of the interrupt vector. 80x86 CPU for the PC, a total of 256 interrupt vectors.
The general process interruption:
When only the main apparatus A, B, C data is ready to deal with it A, B, C, data exchange. When slower peripherals prepare their own data, CPU to perform their usual main program. In this sense, some of the operation of the CPU and peripheral devices are performed in parallel, the program query therefore be compared with the serial, the efficiency of the computer system is greatly improved. As shown below:
The actual interruption process even more complicated, a detailed flowchart illustrating the processing procedure of the interrupt. When the CPU after executing - Article current instruction, if an interrupt request to a peripheral CPU, the CPU response with satisfying the condition, an interrupt is issued in response to the signal, at the same time close the interrupt ( "interrupt mask" flip-flop "1 "), it means that the CPU will not accept another - interruption of devices. At this time, CPU will look interrupt request source which device. And save the contents of CPU its own program counter (Pc) of. It then transferred to process the interrupt source of the interrupt service routine. In the Save CPU information field device (e.g., text data exchange) after. The recovery site information. After the completion of these actions, open interrupt ( "interrupt mask 'flip-flop' o"), and returns to the next instruction of the original network is interrupted main program.
(1) 尽管外界中断请求是随机的，但CPU只有在当前一条指令执行完毕后，即转入公操作时才受理设备的中断请求，这样才不致于使当前指令的执行受到干扰。公操作是指一条指令执行结束后CPU所进行的操作，如中断处理、直接内存传送、取下条指令等 。外界中断请求信号通常存放在接口中的中断源锁存器里，并通过中断请求线连至CPU，每当一条指令执行到末尾，CPU便检查中断请求信号。若中断请求信号为“1”，则CPU转入“ 中断周期”，受理外界中断。(2) 为了在中断服务程序执行完毕以后正确地返回到原来主程序被中断的断点(PC内容)而继续执行主程序，必须把程序计数器PC的内容，以及当前指令执行结束后CPU的状态(包括寄存器的内容和一些状态标志位)都保存到堆栈中去。这些操作叫做保存现场。(3) 当CPU响应中断后，正要去执行中断服务程序时，可能有另一个新的中断源向它发出中断请求。为了不致造成混乱，在CPU的中断管理部件中必须有一个中断屏蔽触发器，它可以在程序的控制下置“1”(设置屏蔽)，或置“0”(取掉屏蔽)。只有在中断屏蔽标志为“0”时，CPU才可以受理中断。当一条指令执行完毕CPU接受中断请求并作出响应时，它一方面发出中断响应信号INTA，另一方面把中断屏蔽标志置“1”，即关闭中断。这样，CPU不能再受理另外的新的中断源发来的中断请求。只有在CPU把中断服务程序执行完毕以后，它才重新使中断屏蔽标志置“0”，即开放中断，并返回主程序。因此，中断服务程序的最后必须有两条指令，即开中断指令和返主指令，同时在硬件上要保证返主指令执行以后才受理新的中断请求。(4) 中断处理过程是由硬件和软件结合来完成的。如在前图中，中断周期由硬件实现，而中断服务程序由机器指令序列实现。后者除执行保存现场、恢复现场、开放中断并返回主程序任务外，对要求中断的设备进行服务，使其同CPU交换一个字的数据，或作其他服务。
轮询方式的基本概念
轮询(Polling)I／O方式或程序控制I／O方式，是让CPU以一定的周期按次序查询每一个外设，看它是否有数据输入或输出的要求，若有，则进行相应的输入／输出服务；若无，或I／O处理完毕柏，CPU就接着查询下一个外设。
所需硬件：外设接口提供状态端口、数据端口
软件机制：应用程序必须定时查询各个接口的状态端口，判断是否需要输入、输出数据，如果需要，则通过数据端口进行数据操作。
特点：CPU通过执行指令主动对外部设备进行查询，外部设备处于被动地位。
上图为一般过程。
轮询方式与中断方式的比较
速度
程序控制方式：
硬件的速度指标：由于“程序控制方式”完全采用软件的方式对外设接口进行控制，所以它的硬件操作只是普通的端口读写，并无特别之处，其速度指标由总线传输速度、端口的响应速度共同决定。
对于这种外设控制方式，速度指标关键在于软件。
中断处理方式：
中断处理方式本身所作的原子操作解释和程序控制方式是一致的。
只不过因为加入了中断请求和响应机制，对状态端口的读取变成了在中断响应过程中对中断号的读取，对状态端口的判断变成了对中断入口地址的确定。
从本质上来说，中断处理方式和程序控制方式本身的速度指标一致，没有大的差别。
可靠性
程序控制方式：
由于硬件不支持中断方式，因此操作系统把CPU控制权交给应用程序后，只要应用程序不交还CPU控制权，操作系统就始终不能恢复对CPU的控制（无定时中断）。应用程序与操作系统都是软件模块，操作系统属于核心模块，它们之间存在交接CPU控制权的关系。正是由于这样的关系，一旦使用对外设的“程序控制方式”时，应用程序出现死锁，则操作系统永远无法恢复对系统的控制。应用程序的故障通过外设控制方式波及到作为核心模块的操作系统，因此，根据关联可靠性指标的计算可知，“程序控制方式”的关联可靠性指标很低。
中断处理方式：
由于提供定时中断，操作系统可以在应用程序当前时间片结束后通过中断服务程序重新获得对CPU的控制权。应用程序的故障不会波及到操作系统，因此，中断处理方式的关联可靠性指标高。
可扩展性
程序控制方式：
由于所有应用程序中都包含对端口的操作，一旦硬件接口的设计发生变化，则所有应用程序都必须进行修改，这会使修改费用升高很多倍。因此，程序控制方式会使相关硬件模块的局部修改指标相对较低。
中断处理方式：
应用程序不直接操作端口，对端口的操作是由中断服务程序来完成的。如果某个硬件接口的设计发生了变化，只需要修改它相关的中断服务程序即可。因此，中断处理方式使得相关硬件模块的局部修改指标较高。
生命期
“程序控制方式”（CPU查询方式）在早期的计算机系统中能够满足应用需求；但是随着外部设备种类的增多、速度差异的加大，这种方式逐渐成为系统性能提高的障碍。它的生命期只限于早期计算机阶段，因为当时外部设备少，且都是低速设备，到8位机出现以后，这种外设控制方式（体系结构）被淘汰。
“中断处理方式”（外设请求方式）能够协调CPU与外设间的速度差异，能够协调各种外设间的速度差异，提高系统的工作效率（速度指标）。使应用程序与外设操作基本脱离开来，降低了程序的设备相关性（关联可靠性指标、局部修改指标）。虽然目前某些快速设备相互间的通信没有通过CPU，也没有使用中断处理方式，但是对于慢速设备、设备故障的处理来说，中断处理方式仍然是最有效的。无论将来计算机系统中的元件怎样变化，只要存在慢速设备与快速CPU之间的矛盾，使用中断处理方式都是适合的。即便不使用中断服务程序，中断的概念也会保持很久。在短时期内，计算机系统还无法在所有领域离开人工交互操作，人的操作速度一定比机器的处理速度慢，因此慢速设备将仍然保持存在（但这不是慢速设备存在的唯一原因）。正因为存在这样的需求，中断处理方式具有较长的生命期。
（转载自：http://www.cnblogs.com/jhxk/articles/1893314.html）