The CPU : arithmetic unit, a controller, a register. (Three core components)
RAM: a memory device of a byte memory cell Cell
NorthBridge ：
32bit 2 ^ 32 = 4GB 32-bit CPU can only understand the physical memory space of 4G
64bit 4GB*4GB
CPU ------ (line multiplexing) addressing ------ RAM
PAE: Physical Address Extension (physical Address Extension) - a on the address bus has 32bit 4bit added
32bit, + 4bit = 64G (32-bit operating system to make the maximum CPU memory space addressed to 64G) - premise: 4bit additional capacity kernel address bus must support.
Now: When your memory is greater than 4G, will directly use the 64bit operating system.
64G Memory: addressability single process is still 3G, 1G addition to the kernel.
Development: multi-threaded single-process model Mysql
CPU access frequency much greater than the RAM, both the speed mismatch, which requires providing a cache.
Buffer: faster storage device than the original, but a small memory
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Replacement strategy: Once the cache can ensure that there is not enough space available and subsequent data they need, when loaded, can be sequential buffer space vacated.
Spatial locality: If the data is accessed, the data is also very close attention to him soon to be accessed. (Improve the hit rate)
Temporal locality: If a piece of data is accessed once, then it may soon be visited once.
After the introduction of the cache, to make up for the huge difference in the speed of the CPU and RAM.
Multi-level cache: the smaller the closer the cache level CPU. Speed closer to CPU speed.
Direct mapping: RAM size of any one memory cell
N-way associative: 1-way associative, 2 way associative, 4-way associative, (full) correlation 8
N-way associative greatly improve the cache hit rate, while ensuring the cache too often not been replaced.
CPU cache by step by step, and ultimately access the data in the cache.
Write-through (Write Through):
Write-back (Write Back): CPU after the update data in the cache, not immediately update it to other levels of cache or main memory to go. When data is discarded, it will be written back to main memory.
Video Card (graphics): both handle a large number of display data that requires both hardware acceleration, there needs to be rendered on the CPU.
Bandwidth and interactivity.
Solid State Drives: Support internal parallel read and write U disk PCI-E
IO Port: 65535 IO device by any IO bus access to the entire computer bus when it must register at the application level to open a number of consecutive IO Port (IO port number)
A system boot, a power-up, BIOS number. . When the self-test is completed, each IO port hardware must apply for registration to the CPU.
Multiplexed bus
Data is returned from the external device is loaded into memory, then the cache memory and there processed by the control CPU.
Pool
Interrupt Controller (Interrupt Controller): CPU help identify equipment that is sent to the interrupt signal.
DMA: Direct memory access, addressing, accessing RAM reserved memory space.
Clock cycle:
Clock:
Monitor (Monitor)
OS----VM
Process (process): a separate operational unit.
System resources: CPU time, memory space
OS : VM
CPU: Time: sliced
Cache: Current program data
If the CPU: 10G (10G clock frequency), a second flip 10G times,
10G so the OS of a virtual CPU into 1G 10 CPU, the one piece together operational unit
Next is the personal understanding of non-positive solution.
Because the CPU, cache, memory speed difference of property, carried out by OS of the CPU time slice, a slice to run a process, thereby reducing differences between them, to avoid waste of resources.
If a process 100 which contains a command, it is executed when the article 73, and give it time to run out. How to know when the next execution of the CPU it will continue to run in Article 74 command.
73：74
This time on the use of internal CPU registers
Instruction counter:
Process switch, to protect the site. Recovery site.
To keep the site ------ ------ main memory
How virtual memory? Multiple processes simultaneously, they will not occupy one another.
Memory chips;
IO device:
----- kernel process
When the CPU has two modes of operation:
If you are running kernel called kernel mode.
When the user processes running on the CPU, called the user mode.
The difference is: the user can not directly control hardware.
Internal CPU, run CPU can command is divided into four layers.
Innermost ring, privileged instruction (kernel)
Address Mapping ---- kernel to wake up processes
Process queue. Process priority priority scheduling ----
Kernel scheduling algorithm time complexity of the process ----- --- O