I. Introduction
Then last updated textbook is the new moon Tang Fei teacher's computer composition principle of the second edition, the last part of the fourth chapter exercises recorded.
Second, the title
1. Suppose the principal memory capacity is 256K words, Cache capacity of 2K words, block 4 length.
(1) Design Cache address format, Cache in how many pieces of data can be loaded?
(2) In a direct mapping mode, the memory address format design.
(3) in the way set associative mapping mode, the memory address format design.
(4) In a fully associative mapping mode, the memory address format design.
(5) If the memory word length is 32 bits, byte addressable memory, write the above mapping modes main memory address format.
answer:
(1) Since Cache capacity 2K = 2 ^ 11 characters, so the word Cache address is 11, and because the block size is 2 ^ 2 = 4, so that the two word block address, block address word Cache 11- 2 = 9, there Cache address format is:
(2) Since the main memory capacity of 256K = 2 ^ 18 characters, so the main memory word address is 18, and because the block address word Cache 9, the address word block 2, the main memory word block labeled 18-9 -2 = 7, the direct mapping mode is the memory address in the format of:
(3) Cache because there are 2K / 4 = 512 blocks and because the four-way set associative mapping each have four, so a total of 512 Cache / 4 = 128 = 2 ^ 7 group, the set of addresses 7, main memory block is marked with the word 18-7-2 = 9, connected to the four main memory address mapping mode is the form:
(4) since the main memory address is 18, and because the two word block address, in accordance with the nature of the whole map is connected, block flag 18-2 winner word = 16 bits, the whole connected to the memory address mapping mode is the format:
(5) of the questions, 32-bit word length memory, addressed by byte, a main memory capacity is 512K words namely 512K × 32/8 = 2 ^ 20B, Cache 2K words capacity several 2K × 32/8 = 2 ^ 13 bits word block length of 4 * 32/8 = 2 ^ 4, so that the two word block address.
Under the direct mapping mode, Cache word block address 13-4 = 9, main memory word block labeled 20-9-4 = 7, a main memory address format is:
is connected to the four mapping mode, Cache block That number is 512/4 = 512 ^ 128 = 2 7 groups, main memory word block flag 20-9-4 = 9, a main memory address format:
the whole is connected to the mapping mode, main memory word block labeled 20-4 = 16, a main memory address format is:
2. assuming a total access Cache hit 4800 when the CPU executes certain programs access main memory 200 hits, is known in the Cache 30ns access cycle, main memory access cycle is 150ns, seeking Cache hit rate and average access time and efficiency Cache- main memory system, how to improve the performance of the system, how many times?
answer:
(1) = 4800 hit ratio H / (4800 + 200 is) = 96%
(2) the average access time = 0.96 × 30 + Ta 0.04 * 150 = 34.8ns
(. 3) access efficiency = 30 /34.8 = 86.2 E%
(. 4 ) of 150 / 34.8 = 4.31 have improved 4.31 --1 = 3.31 times
3. The main memory capacity is provided 1MB, direct mapped Cache embodiment capacity of 16KB, the block length is 4KB, each 32-bit word. How ABCDEH main memory address of the storage unit where in the Cache?
answer:
(1) a problem, because the main memory addressing and byte Cache,
the Cache capacity 16KB = 2 ^ 14B, i.e., a total address format 14 and the block length of 4 × 32/8 = 16B = 2 ^ 4B, i.e., the word block address 4, Cache address format as:
(2) since the main memory capacity of 1MB = 2 ^ 20B, so that address total format is 20 bits, and because Cache word block address 10, the word block address 4, so direct mapping mode, the main memory word block labeled 20-14 = 6, the main memory address format is:
(3) main memory address ABCDEH = 1010 1011 1100 1101 1110B, main memory word block is marked as 101010, Cache word block address is 1111001101, the block address word is 1110, so the main memory unit to be mapped to the Cache 101 010 1110 byte, i.e. byte 14 of the first 42 positions. Cache or the first 11 1100 1101 1110 = 3CDEH byte position.
4. The disk group disk 6, the outermost sides of the disk may be recorded, a storage area of 22cm internal diameter, an outer diameter of 33cm, the track density of 40 / cm & lt, the inner density of 400 / cm & lt, speed 3600 rev / min, Q :
(1) the total number of available storage surface?
(2) the total number of cylinders?
(3) The total disk storage capacity is how much?
(4) data transfer rate is the number?
answer:
(1) a total of 6 × 2 = 12 storage surface
(2) Total number of cylinders:
an effective storage region = (33-22) /2=5.5cm
cylinders: = 40 / cm × 5.5cm = 220 Road
( 3) total storage capacity:
an inner circumference track = 22 × 3.14 = 69.08cm
channel capacity = 400 / cm × 69.08cm = 3454B
surface channel capacity = 3454B × 220 = 759,880B
disk group, the total capacity = 759,880B × 12 = 9118560B
(. 4) speed of 3600 r / min = 60 revolutions / second
transmission rate 207.24 thousand B = 60 × 3454 / S
5. The disk storage a revolution speed of 3,000 rev / min, a total of four recording surfaces, each of 5 mm, per 12288 bytes recorded information track, the minimum track diameter of 230mm, a total of 275.
Q:
(1) How much disk storage capacity?
(2) highest density and lowest bit density is how many?
(3) Disk data transfer rate is the number?
(4) The average waiting time is how much?
answer:
(1) the storage capacity of 275 × 12288 ×. 4 = 13.5168 million B
(2) highest density of 12288 / (3.14 × 230) ≈ 136 bit / mm
lowest bit density 12288 / (3.14 × (230 + 2 × 275/5)) ≈ 92 / mm
(. 3) disk data transfer rate of 12288 × 3000 r / min = 12288 × 50 rev / sec 614400 B = / S
(. 4) average waiting time 1/50/2 = 10ms
