45、受信機は、実装されたシリアルポートUARTを解析します

シリアルを受け取ることができます。

1. 波形解析によると、解析プロセス。
2. 同期信号、及びFレジスタを分析します。
3. サンプルレジスタrの分析。
4. ハンドシェイクインタフェース信号。
5. シミュレーションプラットフォームを書くだけでなく、実行されます。

   
   
   
   /*
   
   uart_rx #(
   	.BAUDRATE ( 115200 ), 
       .FREQ ( 200000000 )
   )uart_rx(
   .clk(  ),
   .nrst(  ),
   .rxd(  ) ,
   .q(  ) ,
   .ready(  ) ,
   .valid(  ) 
   );
   
   */
   
   
   module uart_rx #(
       parameter BAUDRATE = 115200, 
       parameter FREQ = 200000000
   )(
   input clk,nrst,
   input rxd ,
   input parity_type,
   //0 NONE
   // 1  odd
   //2 EVEN 
   output  reg [7:0] q ,
   input ready ,
   output reg valid 
   );
   
   reg [31:0] c ;
   reg [7:0] st ;
   reg [2:0]  rxdr;
   reg f;
   
   always @(posedge clk)rxdr[2:0]<={rxdr[1:0],rxd};
   wire negedge_of_rxd = rxdr[2:1] == 2'b10 ;//下降沿
   
   wire half_bit_syn =( c == ((FREQ / BAUDRATE )/2-1 ) ) ;
   
   always@ (posedge clk)
   if (~nrst)begin f<=0;c<=0;end 
   else case (st)  
   0:begin f<=0;c<=0;end 
   default if (half_bit_syn) begin f <= ~f ;c<= 0;end else c<=c+1 ;
   endcase 
   
   
   wire bit_sample = half_bit_syn & (~f)  ;
   
   reg [7:0]r ;
   always @(posedge clk)if (~nrst) st<=0;else 
   case (st)
   0: if (negedge_of_rxd)   st<= 1 ;//  wait negedge of rxdr;
   1: if (bit_sample)if (rxdr[2])st<=0;else st <= 2 ; // check if a start flag 
   2: if (bit_sample) st<=3;  // bit 0
   3: if (bit_sample) st<=4;  // bit 1 
   4: if (bit_sample) st<=5;  // bit 2 
   5: if (bit_sample) st<=6;  // bit 3 
   6: if (bit_sample) st<=7;  // bit 4 
   7: if (bit_sample) st<=8;  // bit 5
   8: if (bit_sample) st<=9;  // bit 6
   9: if (bit_sample) st<=10; // bit 7
   10: if (bit_sample)  //parity_bit 
   case (parity_type)
   1 : st <= (rxdr[2] != ^r[7:0]) ? 11:12; //odd
   2 : st <= (rxdr[2] == ^r[7:0]) ? 11:12; //even 
   default :st <= 11 ;endcase 
   11 : if (bit_sample)  st <= 13 ; // legal value 
   12 : if (bit_sample)  st <= 13 ; // illegal value 
   13 : if (bit_sample)  st<=0;   //stop bit 
   default st<=0;
   endcase   
    
   always @ (posedge clk )if ( st==2) r[0]<= rxdr[2]; 
   always @ (posedge clk )if ( st==3 )r[1]<= rxdr[2]; 
   always @ (posedge clk )if ( st==4 )r[2]<= rxdr[2]; 
   always @ (posedge clk )if ( st==5 )r[3]<= rxdr[2]; 
   always @ (posedge clk )if ( st==6 )r[4]<= rxdr[2]; 
   always @ (posedge clk )if ( st==7 )r[5]<= rxdr[2]; 
   always @ (posedge clk )if ( st==8 )r[6]<= rxdr[2]; 
   always @ (posedge clk )if ( st==9 )r[7]<= rxdr[2]; 
    
   /*
   always @ (posedge clk )if (bit_sample  && st==2 )r[0]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==3 )r[1]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==4 )r[2]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==5 )r[3]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==6 )r[4]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==7 )r[5]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==8 )r[6]<= rxdr[2];
   always @ (posedge clk )if (bit_sample  && st==9 )r[7]<= rxdr[2];
   */
   
   
   always @ (posedge clk )
   if (~nrst) valid<=0;else if (st==11 & bit_sample )valid<=1;
   else if (ready)valid<=0;
   
   always @ (posedge clk )if (~nrst) q <=0;else if (st==11)q<=r;
   
   endmodule