STM32F4x_interrupt configuration

STM32F104x – Summary of interrupt configuration

learning target:实现 “中断分组设置 + 中断优先级管理”；

• 1. Set interrupt grouping when the system starts running.
  Determines the group number, that is, the number of allocated bits that determine the preemption priority and response priority . The calling function is NVIC_PriorityGroupConfig();
• 2. Set the interrupt priority level of the interrupt used. The function called for each interrupt is NVIC_Init();

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Learning Content:

NVIC 中断管理函数主要在 misc.c 文件里面

1.1 中断分组配置

void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
    
    
 	assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
 	SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;                       //过设置 SCB->AIRCR 寄存器来设置中断优先级分组
}

• Disassembly analysis: Double-click to select "IS_NVIC_PRIORITY_GROUP" in the function body and then right-click "Go to definition of ..." to view the entry parameter structure

#define IS_NVIC_PRIORITY_GROUP(GROUP)                      \\分组范围0-4
(((GROUP) == NVIC_PriorityGroup_0) || 
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))

• Example: Set the system interrupt group priority to 3

NVIC_PriorityGroupConfig(NVIC_PriortyGroup_2);       // 可屏蔽中断的IP寄存器组的高四位中，最高3位是抢占优先级，低1位是响应优先级

• Interrupt priority rules:Preemption priority > response priority, and the smaller the value, the higher the priority.

❗Note:

1. If the preemption priority and response priority of the two interrupts are the same, then it will be executed first depending on which interrupt occurs first;

2. A high-priority preemption can interrupt an ongoing low-priority preemptive interrupt; while preempting an interrupt with the same priority, a high-priority response cannot interrupt a low-priority response interrupt.

1.2 中断优先级管理

void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);              //中断初始化函数

• NVIC_InitTypeDef structure analysis

 typedef struct
{
    
    
 	 uint8_t NVIC_IRQChannel;                       //在 stm32f10x.h 中找到每个中断对应的名字。例如 USART1_IRQn
	 uint8_t NVIC_IRQChannelPreemptionPriority;     //定义这个中断的抢占优先级别;
 	 uint8_t NVIC_IRQChannelSubPriority;            //定义这个中断的(响应优先级子优先级别)
 	 FunctionalState NVIC_IRQChannelCmd;            //该中断通道是否使能
} NVIC_InitTypeDef;

• Example: Enable the interrupt of serial port 1, set the preemption priority to 1, and the response priority to 2, the initialization method

	NVIC_InitTypeDef NVIC_InitStructure;
	NVIC_InitStructure.NVIC_IRQChannel  = USART1_IRQn;               //串口中断1
	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;        //抢占优先级为1
	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2；              //响应优先级为2
	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE；                 //IRQ通道使能         
	NVIC_Init(&NVIC_InitStructure);                                  //根据上面指定的参数初始化 NVIC 寄存器

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Basic review:

The CM4 core supports 256 interrupts, including 16 core interrupts and 240 external interrupts, and has 256 levels of programmable interrupt settings. But STM32F4 does not use all the things of the CM4 core, STM32F40xx/STM32F41xx has a total of 92 interrupts.
STM32F40xx/STM32F41xx 的 92 个中断里面，包括 10 个内核中断和 82 个可屏蔽中断，具有 16 级可编程的中断优先级，而我们常用的就是这 82 个可屏蔽中断。

The register structure related to NVIC in MDK is defined as follows:

typedef struct
{
    
    
 	__IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
	 	uint32_t RESERVED0[24];
 	__IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
		 uint32_t RSERVED1[24];
	 __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
		 uint32_t RESERVED2[24];
	 __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
 		uint32_t RESERVED3[24];
 	__IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
 		uint32_t RESERVED4[56];
 	__IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
 		uint32_t RESERVED5[644];
 	__O uint32_t STIR; /*!< Software Trigger Interrupt Register */
} NVIC_Type;

• ISER[8]: Interrupt Set-Enable Registers interrupt enable register group, if you want to enable an interrupt, you must set the corresponding ISER bit to 1;
• ICER[8]: Interrupt Clear-Enable Registers Interrupt disable register group, the function is opposite to ISER, used to clear the enable of an interrupt;
• ISPR[8]: Interrupt Set-Pending Registers Interrupt pending control register group, by setting 1, the ongoing interrupt can be suspended, and the interrupt of the same level or higher level can be executed
  . Writing 0 is invalid;
• ICPR[8]: Interrupt Clear-Pending Registers Interrupt unpending control register group, the function is opposite to ISPR, setting 1 can unpend the pending interrupt, writing 0 is invalid;
• IABR[8]: Interrupt Active Bit Registers Interrupt active bit register group, the corresponding position is 1, indicating that the interrupt corresponding to this bit is being executed. Through it, you can know which interrupt is currently being executed, and it will be automatically cleared by the hardware after the interrupt is executed.
• ❗ IP[240]: Interrupt Priority Registers interrupt priority control register group, IP[81]~IP[0] correspond to interrupt 81~0 respectively, the 8bits occupied by maskable interrupts are not all used, but only the high 4 bit. These 4 bits are further divided into preemption priority and response priority. The priority of preemption comes first, and the priority of response comes later.