The basic concept of SCM
The composition of SCM 1.1
A CPU, RAM (random access memory), ROM (Read Only Memory), I / O interfaces, and an internal functional components.
1.2 MCU internal data transmission
MCU internal bus data transmission is completed, after a tri-state gate when the input data, three-state gate hung on the bus, as an input when necessary, maintained at the low potential, the output potential is high. Microcontroller 51 has an internal address bus 16, the address bus and related to the ability of the microcontroller, the corresponding relationship is: the microcontroller to be able to find the number of the address bus power = 2.
1.3 The concept of register
Register is limited storage capacity high-speed storage means, they can be used for temporarily storing commands, data and addresses.
Register composed of flip-flops, a buffer register for temporarily storing data for input to RAM or I / O port, e.g. SBUF.
1.4 single-chip CPU system
CPU: It is for the measurement and control in accordance with the object, embedded and structural requirements single chip, designed to ensure outstanding control.
System clock: meet the CPU and the circuit chip on each unit clock.
Reset circuit: to meet the power-on reset, the most simplified circuit reset signal.
Bus control logic: to meet the control of CPU internal bus and the external bus.
Internal bus control units coordinate operation for realizing the circuit chip; external bus when a control for operating the microcontroller managing peripheral expansion.
1.5 input and output interface I / O
An input / output device connected to the outside, measurement and control object.
1.6 the SFR
SFR is the internal management and control of the microcontroller I / O port, the basic functional units, the register function expansion unit is running.
By programming the SFR, the manner provided, the read start operation and status and the like.
1.7 internal bus
A common communication channel to transfer information between the microcontroller and the functional modules within the CPU. Into the data bus DB (Data Bus), an address bus AB (Address Bus) and a control bus CB (Control Bus).
Data bus: bidirectional, for transmitting data to achieve the CPU memory, I / O interfaces, the exchange of information between functional blocks, the direction depending on whether a read or write operation.
Address bus: one-way, the address information is sent by a CPU, is used to access the memory and I / O interfaces.
Control Bus: unidirectional, or transmit timing control signal. Such as read / write signals, interrupt request signal, a reset signal. Each signal has its own function, control of the microcontroller and orderly use of the work.
1.8 MCU 51 and MCU structure classification
Special type of microcontroller 51
The internal structure of the microcontroller 51
The definition of each pin microcontroller
Wherein the composition of the pin and each pin function as follows:
1. Composition:
the I / O pins: four groups of eight.
Control pins: four
clock pins: two
power supply pins: 2
2. Function
P1 port is a standard I / O port, no special function.
It may be used as a quasi-P0 port I / O port, but have an external pull-up resistor; when external memory may also be multiplexed with the lower 8-bit address bus (AB) and a bidirectional data bus (DB).
P2 can be used as a quasi-port I / O port, can be used as the upper 8-bit address bus (AB) when the external memory.
P3 each pin has a second function, both alone as a standard I / O port or the second function, can also be used in combination, which is about a few as I / O port, the other functions as a second port.
EA pin is used as an external memory function of opening and closing, using the internal memory when the pin is left floating or connected to high level, the external memory can be accessed only then low.
RST is a reset pin, when the pin voltage level for two periods can be reset.
1.9 end parallel I / O port structure
Each of the following figures shows only one each I / O mouth.
1.P1 port internal structure
P1 port has only a standard I / O port function, so to analyze when required the output data, the control tri-state gate is at a high potential, a tri-state gate is low. An internal bus to send data to the D terminal of the latch, the latch is operating normally (the latch is actually a D type flip-flop, when the clock pulse is input to CP, Q is equal to a sub-state end state D ), if the output is 1, the process is as follows, firstly to the D terminal 1, such as a Q terminal, the non-Q terminal is 0, so the field effect tube as at the rear, by the VCC to GND of the circuit is not turned on, so that the outlet voltage is high, so the output 1, if the output 0, Q 1 is a non-terminal, the FET is turned on, the outlet voltage is pulled down, so that the output is 0. When the required data is entered, the control tri-state gate 1 is opened, but if the input operation is performed before, already once output 0, so will the non-Q terminal of latch 1, the FET is turned on, will cause the port has been pulled low, resulting in not correctly input data, thus the input operation is performed before, 1 should output.
2.P2 end of the internal structure:
Compared to the port P1, P2 port more than one control line for controlling the multiplexer MUX to select the function, for general I / O multiplexer is used when an end switch, when placed in an end address, is used The second function. Analytical method with P1.
3.P3 port internal structure
Compared to the port P1, P3 port and a plurality of NAND gates, when / O as a normal I, the second pin remains high, when the second function is used to output the latch terminal Q set (i.e. output 1, output 1 are required to performing other input port), a data output function determined by the second end. If a second function input, a second input through a dedicated input port.
4.P0 end of the inner structure
The port P1 analysis method as previously described, except that the port is not internal pull-up resistor as a general purpose I / O port, need an external pull-up resistor.
1.10 microcontroller memory structure
1-chip memory
The structure can be subdivided into
Lower left is 128-bit address, which is the working register 00H to 1FH area, divided into four groups, each group can be divided into eight address R0 to R7, when the program calls, e.g. MOV A, R0, but can not determine the R0 this is a storage area that four working groups, in fact, in the special function register PSW in the third data and to determine the fourth bit, if it is 01, compared with the first group, so the rest (any one time , can only use a register bank; after CPU reset, the default selection group 0). 20H to 2FH bit-addressable memory area, every Boolean i.e. each of these address 16 addresses can be changed directly in the value, for example 20.3H would be represented as the number of address 20H 4. 30H to 7FH data buffer, basically can not use. The right of the address region 128 is high, in addition to the 21 address register 18 special function can directly access, none of the remaining rows. When the special function address register is 0 or end 8 (i.e. divisible by 8), then the special function register can be bit addressable.
Special Function Register Address follows:
2. chip memory
1.11 MCU reset
1. The state of each register after reset microcontroller
2. The reset circuit
1.11 low-power operation mode
1. In standby mode of operation
2. The power-down mode of operation
Standby operation mode features:
Standby work settings:
Power-down mode features:
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