Fun privileged students Zynq serial 45 - [ex64] MT9V034 camera image sharpening process Laplacian
1 System Overview
As shown, this is the overall block diagram of a video capture system. Initial power, FPGA register is required by the initial configuration of the CMOS Sensor IIC interface. These basic parameters initialized, i.e., initialization initialization data corresponding to the address is stored in a pre-configured within the FPGA chip ROM good. After the initial configuration, CMOS Sensor can continuously output a standard RGB video data stream, FPGA by its synchronizing signal, such as a clock, line and field frequency is detected, so that the real-time image data acquired from the data bus. MT9V034 default initialization camera can output normal video data stream, and therefore the FPGA practically without any initial configuration IIC.
Inside the FPGA, to capture video data through a FIFO, to convert the data stream synchronized to the original frequency of 25MHz at a frequency of 50MHz. This data is then fed into the re-write cache DDR3 asynchronous FIFO, the data in this FIFO once they reach a certain number, it will AXI HP0 DDR3 bus write through. At the same time, AXI HP0 DDR3 cache bus will read image data into the FIFO buffer, and finally sent to the LCD display driver module. LCD driver module continually requesting read image data, and drives the liquid crystal display to display a video image.
In addition to this example, the aforementioned image flow and do show DDR3 cache, but also prior to DDR3, do additional image line buffer and the plurality of Laplacian sharpening processing the original image to the original image buffer to obtain a new sharpened after this image stream is written to via the AXI HP1 DDR3 bus. AXI HP1 bus request will be based on the LCD display module, the image reading processing is displayed. Finally on the VGA liquid crystal display, can see the left image is the original image, the right image is the image after the sharpening process.
2 image sharpening Laplace
2.1 基本概念
在图像增强中，平滑是为了消除图像中噪声的干扰，或者降低对比度。与之相反，有时为了强调图像的边缘和细节，需要对图像进行锐化，提高对比度。
拉普拉斯锐化图像是根据图像某个像素的周围像素到此像素的突变，也就是说它的依据是图像像素的变化程度。我们知道，一个函数的一阶微分描述了函数图像是朝哪里变化的，即增长或者降低；而二阶微分描述的则是图像变化的速度，急剧增长下降还是平缓的增长下降。那么据此我们可以猜测出依据二阶微分能够找到图像的色素的过渡程度，例如白色到黑色的过渡就是比较急剧的。
或者用官方点的话说：当邻域中心像素灰度低于它所在的领域内其它像素的平均灰度时，此中心像素的灰度应被进一步降低，当邻域中心像素灰度高于它所在的邻域内其它像素的平均灰度时，此中心像素的灰度应被进一步提高，以此实现图像的锐化处理。
2.2拉普拉斯（laplace）算子
最常用的无方向性的二阶差分算子，其模板有33、55和77等多种形式。。
例如，以33算子为例，1~8像素是（x,y）点周围邻近的8个像素点。可以使用右侧的2种模板对（x,y）以及周边4或8个像素点进行运算，替代原来的（x,y）点。
当然了，根据中心点的权重程度，也可以使用如下2中模板来实现图像锐化。
2.3 Matlab实现
基于第一种拉普拉斯锐化处理，我们的Matlab代码如下：
clear
clc
I1=imread(’.\lena.jpg’);
I=im2double(I1);
[m,n,c]=size(I);
A=zeros(m,n,c);
%for R
for i=2:m-1
for j=2:n-1
A(i,j,1)=I(i+1,j,1)+I(i-1,j,1)+I(i,j+1,1)+I(i,j-1,1)-4*I(i,j,1);
end
end
%for G
for i=2:m-1
for j=2:n-1
A(i,j,2)=I(i+1,j,2)+I(i-1,j,2)+I(i,j+1,2)+I(i,j-1,2)-4*I(i,j,2);
end
end
%for B
for i=2:m-1
for j=2:n-1
A(i,j,3)=I(i+1,j,3)+I(i-1,j,3)+I(i,j+1,3)+I(i,j-1,3)-4*I(i,j,3);
end
end
B=I-A;
%output
imwrite(B,‘lena.tif’,‘tif’);
imshow(’.\lena.jpg’);title(‘origin image’);figure
imshow(‘lena.tif’);title(‘image after laplace transform’)
滤波效果如下。
Matlab源码、Lena.jpg原图和比对图存放在project\zstar_ex64\matlab文件夹下。
3 FPGA-based image smoothing
project folder project \ zstar_ex64 \ zstar.srcs \ sources_1 \ laplace_transform.v achieve a new module in the Laplace sharpening process. The functional block diagram is used two the FIFO, for buffering longitudinal rows, three data streams enter into the image processing are the image of the n-1 th, n-th row and row n + 1, the control input data stream and two image FIFO buffer in the same location, register values before and after the image pixels are two caches, so that the center pixel can be realized and the preceding column, data synchronization processing between the uplink and downlink.
4 assembly instructions
MT9V034 camera module is connected to the board through the developing Zstar Zynq Zstar ISB plate (P3), VGA is also connected through the backplane Zstar ISB Zstar Zynq development board, VGA board also need to be connected to a VGA monitor. Connection schematically shown in FIG.
5 board-level debugging
of the present example corresponds ex64 example project, has produced a good BOOT.bin placed in the project path "zstar_ex64 \ zstar.sdk \ BOOT". You can also refer to the document "Fun Zynq- example piece: [ex51] BOOT.bin.pdf startup file production program running naked" file produced comprising BOOT.bin .bit file, copy it to the TF card inserted development Zstar slot plate, well fitting connection, the power can be seen VGA display simultaneously displays the left and right images, a left image is the original image, the right image is the image sharpening process.
