High fan-out net is a common bottleneck timing closure. Therefore, in addition to the traditional method of reducing fan-out, the net may also be incorporated BUFG, provided that there is available BUFG. As we all know, BUFG is a global clock resources when configuring MMCM or PLL will be used. Here, I'll introduce two ways you can method BUFG through the rational use MMCM / PLL savings.
In most cases, MMCM Network Clock Skew as removal mode (Clock Network Deskew), as shown below. In this mode, as the clock frequency will be combined with an effective method BUFG savings. With the frequency divided clock may be from the same MMCM, it may come from different MMCM. We need to consider the requirements for the system clock phase relationship when combined. Below, the same phase endpoint 1,4,6, 2,3,5 same phase.
Note: Source ug572, figure 3-9
BUFG Another way to save is to work under the MMCM in INTERNAL mode. As shown below. In this mode, MMCM is used purely as a frequency synthesizer, you do not care about the phase relationship between the input clock and output clock MMCM. At this point, CLKFBOUT directly to the CLKFBIN, you can save a BUFG.
Notably, when you MMCM as INTERNAL mode, corresponding to the IP Core Phase Alignment not checked, as shown in FIG.
