Transfer: https://blog.csdn.net/a617996505/article/details/82386952
1.LVDS interfaces the data format classified with the
single 6it LVDS
Such an interface circuit, the use of single mode transmission, each of the primary color signals using the 6-bit data of 18-bit RGB data, therefore, also known as 18 or 18bit LVDS interfaces. This, also known as 18 or 18bit LVDS interface.
Dual 6bit LVDS
Such an interface circuit, the use of dual mode transmission, each of the primary color signals using the 6-bit data, wherein the odd channel data of 18 bits, even 18-bit data path, 36-bit RGB data, therefore, also known as 36 or 36bit LVDS interface.
Single 8bit LVDS
Such an interface circuit, the use of single mode transmission, each of the primary color signals using 8-bit data of 24-bit RGB data, therefore, also known as 24-bit or 24bit LVDS interfaces.
Dual 8bit LVDS
This interface circuit, using dual transfer mode, each 8-bit data primary color signals, wherein the odd channel data is 24 bits, 24-bit even channel data, 48-bit RGB data, therefore, also known as 48 or 48bit LVDS Interface
Now the market is basically 8bit and 6bit screen,
LVDS interface circuit, converts the parallel data format to serial data pixels there are two main standards: VESA and JEIDA
1) VSEA standard format as shown below:
The above picture is a single of the VESA standard signal, a line of data input is more 2bit.
Dual signal format on this can give an example:
The above picture is VSEA standard signal of dual 8bit.
2) JEIDA standard was developed by the Japan Electronic Industry Development Association (JAPANELECTRONIC INDUSTRY DEVELOPMENT ASSOCIATION) standard, the format is as follows:
Referring view can be compared, if the pixel is 6bit RGB, then each channel requires only the top three pairs of data lines, wherein R9 ... R4, G9 ... G4, B9 ... B4 corresponding to the actual R5 ... R0, G5 ... G0, B5 ... B0; Similarly, if the pixel is 8 bit RGB, then each channel simply to rely on the data line 4 above, wherein R9 ... R2, G9 ... G2, B9 ... B2 corresponding to the actual R7 ... R0, G7 ... G0, B7 ... B0.
FIG correlation signal has substantially datesheet on each screen.
These signals may be substantially Analyzing FIG: 1. Mono passage;
2. What is the bit RGB;
3. The format of the data signal;
View IMX6Q_LDB Control Register, there are settings:
1. Mono Road;
2. What is the bit RGB;
3. The format of the data signal;
There device tree kernel can directly modify the operating device tree to three parameter register, to modify the red part of:
&ldb {
status = "okay";
dual-mode = <1>; // this is a split-mode should be set to single LVDS, dual = <1>;
lvds-channel@0 {
fsl, data-mapping = "spwg"; // this is a data format (VESA), there is a criterion of JEIDA
fsl, data-width = <24>; // this is a data bit, i.e., 8bit RGB
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>; // pixel clock
hactive = <1280>; // horizontal number of pixels
vactive = <800>; // vertical number of pixels
hback-porch = <10>; // the horizontal direction
hfront-porch = <30>; // horizontal front porch
vback-porch = <2>; // rear vertical edge
vfront-porch = <4>; // vertical front porch
hsync-len = <10>; // line synchronization pulse
vsync-len = <6>; // vertical sync pulse
};
};
};
Here's how we should fill in the blue part of the analysis.
2. Screen parameter settings (blue)
fb_videomode significance of various parameters
Abstract of the parameters as shown below:
The significance of each member fb_videomode Comments:
name
Data sheet referred to
Chinese name
significance
Remark
(Abbreviation or another name)
name
No
first name
LCD screen name (optional)
No
refresh
No
Refresh rate
Refresh Rate (kernel many examples are assigned to 60)
No
xres
No
Line width
The number of pixels per line
No
yres
No
Screen height
The number of lines of the screen
No
pixclock
No
Pixel Clock
The length of each pixel clock period, in units of picoseconds (negative 12th power per one second is 10)
No
left_margin
HBP
Level back porch
The number of pixel data in each row or column to be inserted at the beginning of the output pixel clock cycles
No
right_margin
HFP
Horizontal front porch
In each row or each column of pixels to the pixel clock count between the end of the output line clock pulses LCD
No
upper_margin
VBP
Perpendicular to the trailing edge
After the vertical synchronization period when the number of invalid line at the beginning of the frame
No
lower_margin
VFP
Vertical front porch
The present frame data to the output end of the invalid line before the start of the next frame is the number of vertical synchronizing cycle
No
hsync_len
HPW
Horizontal sync pulse width
Unit: pixel clock cycle
HWH(HSYNC width)
vsync_len
VPW
Vertical sync pulse
Unit: The time line of th
HWH(HSYNC width)
sync
No
Sync polarity setting
Can (vertical synchronization active high) is provided as needed FB_SYNC_HOR_HIGH_ACT (active high horizontal synchronization) and FB_SYNC_VERT_HIGH_ACT
No
vmode
No
No
Most of the examples in the kernel directly set FB_VMODE_NONINTERLACED. interleaving means interlaced [interlaced] scan, television, 2: 1 interlace, i.e., two fields per frame, two vertical scanning, a scanning odd lines, and the even-numbered scanning lines another. Obviously this is not the current mode LCD.
No
flag
No
No
There are currently no see usage
No
Can be obtained from the chart:
Horizontal total cycle = left_margin + right_margin + hsync_len
Vertical total cycle = upper_margin + lower_margin + vsync_len
The following mainly 16BPP TFT screen as an example. Some LCD will give a list of parameters, such as the figure below, you can clearly find the parameters needed in the red box, take the "type" typical value. Some LCD but not directly give such a list, set some parameters are not given, it needs to be determined by the timing chart.
Below 3.5-inch TFT LCD screen TM035KDH03 Pegasus is an example to explain.
Parameter calculation:
LCD can be seen that the clock is 28M, so pixclock = 1000000/28, in the device tree is clock-frequency = <28000000>;
Line sync pulse width is one clock cycle, therefore, hsync_len = 1
Sync pulse width of the field is one line period, therefore, vsync_len = 1
The figure is a timing chart showing an image. The figure shows, up_margin = 13-1 = 12 ,, yres = 240,
263 throughout the field period, so lower_margin = 263-13-240 = 10
Also see, column synchronization signal active high, horizontal sync signals are active high.
The figure is a timing chart of a line.
Can be seen, left_margin = 69, xres = 320, right_margin = 408 -320 - 70 = 18
The rising edge of the data valid output enable is active high.
Total at the above parameters, the following results were obtained:
static struct clcd_panel conn_lcd_panel = {
.mode = {
.name = "QVGA TM035KDH03",
.refresh = 60,
.xres = 240,
.yres = 320,
.pixclock = 35714,
.left_margin = 69,
.right_margin = 18,
.upper_margin = 12,
.lower_margin = 10,
.hsync_len = 1,
.vsync_len = 1,
.sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
}
So with the device tree can write:
clock-frequency = <28000000>; // pixel clock
hactive = <240>; // horizontal number of pixels
vactive = <320>; // vertical number of pixels
hback-porch = <18>; // the horizontal direction
hfront-porch = <69>; // horizontal front porch
vback-porch = <10>; // rear vertical edge
vfront-porch = <12>; // vertical front porch
hsync-len = <1>; // line synchronization pulse
vsync-len = <1>; // vertical sync pulse
3. Frequently Asked Questions debugging process
1. backlight
Debugging is first necessary backlit screen, backlit screen does not light up what can be displayed, according to the specifications of the backlight is lit, hardware engineers can seek help
2. scattered on the screen
when debugging, somehow we will find bits and pieces on the screen, usually in this case, we first have to see if the VGH and VGL voltage is within the range described in the datasheet. If it is within the standard range, but still bits and pieces, it is likely that timing issues. This time may wish to change the timing of sampling in the code (such as rising sampling instead falling sampling). If you can not change the code, you can also add a 100R resistor clk signal line may also resolve the issue.
3. Display jitter
After confirming VPW, VBP, VFP, HPW, HBP, HFP setting LCD specifications have been met, if the screen display is still dithering, then, might the frequency of the output clock signal is reduced, it is possible to solve the problem.
There is also a phenomenon LVDS signal line voltage higher specifications that will also appear. There have been LVDS signal voltage is 5V 3.3V led to the emergence of small radio display screen jitter.
4. display the video
Huaping phenomenon, in theory, lead to a RGB is not fine. The number of color bits, due to color sequential.
Color format specification section to check whether the RGB888 format settings become 666, or order of RBG, BGR and the like are possible.
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