[Verilog_3]: to design a prescaler, the division ratio of maximum 100,000

Design can be a prescaler, the division ratio of a maximum of 100,000

Design a preset frequency divider with a maximum frequency dividing coefficient of 100000.

author : Mr.Mao
e-mail : [email protected]

module freq_div
#(
	parameter N = 17 
)
(			
	input clk,
	input reset_n,
	input [N-1:0] period_param,  //周期
	input [N-1:0] duty_param,   //占空比
	output reg div_out
);
	reg [N-1:0] cnt;
	
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			cnt <= 0;
		else if(cnt < period_param-1)
			cnt <= cnt + 1'b1;
		else
			cnt <= 0;
				
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			div_out <= 0;
		else if(cnt < duty_param-1)
			div_out <= 1'b1;
		else 
			div_out <= 0;

endmodule 
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Origin blog.csdn.net/qq_43403025/article/details/104092630