Background: In this article, will from paging segmentation mechanism to resolve Linux memory management system works, because Linux memory management is too complex and limited capacity. I will try to summarize their part to write clearly.
From real mode to protected mode addressing different:
CPU 16-bit addressing mode: In the CPU-8086, provides two addressing registers, respectively, segment registers (e.g., CS, DS, SS) and the segment offset register (e.g., SI, DI, SP). And the length of these types of registers are 16bit, addressing is very simple: cs: ip = (cs << 4 + ip). That value cs register is shifted left 4 ip is worth to add a physical address (physical address is real value in memory).
32-bit addressing mode of the CPU: CPU in the 80X86, there is provided a segmentation and paging . For addressing the CPU, the CPU is so-8086 will no longer segment register segment offset register direct calculation result obtained.
1) So how are addressed in the 32-bit CPU in it?
i) How many tabs segmented mode?
It is to introduce first register CR0 (below):
For CR0 speaking, there are two bit:
PE bit: should the set (1) is enabled on the protection (segment) mode.
Bit PG: PE bit in the set of precondition PG indicates open paging mode.
How ii) addressing the segmentation mechanism (obtained linear address )?
Description: segment register (e.g. CS) there is an index (index) which, it will find a table (GDT) register according GDTR, then there are the table element, comprising an internal element segment base. And this segment base address plus the value of the index register section directly obtained value of the linear address.
Details:
After opening the split mode, meaning the value of a segment register which is no longer simply a segment base address of (i.e. (cs << 4) to give segment base), the current value is called a segment register load segment selector , structured as follows:
We can see there is a bit composed of several descriptor index (that is, briefly mentioned in the index) , as well as TI and RPL bit (but do not ignore it).
GDTR:
See GDTR and the IDTR (GDTR fact, this is similar to another register) is a linear base address and the table length composition, that is to say the linear base address of the head table where the linear base address (like an array name ), table length is the length of the table of friends.
So naturally we can get a similar array (consisting of consecutive addresses) of the table.
For this "array", its elements are called descriptor :
I can see a long segment descriptor (a total of 64bit) ... but never mind, the moment we just need to be divided into three parts: the base address, segment limit long segment attributes. It can be. (The reason here segment base address and limit what long divided into several parts mainly because of problems left over by history, but it does not matter, they just need to put together several separate can get a real base address of the segment) .
The segment base so obtained, we naturally its value within the index register segment is obtained by adding the linear address of the!
iii) how the paging mechanism for addressing (get physical address )?
Should we start page, then it means we've got a linear address (paging is carried out on the basis of segmentation).
简述 : 首先我们把线性地址分为几个部分,目录(本质是页目录表的索引),页面(本质是页表的索引),页内偏移(本质是偏移量)。
由 CR3寄存器 作为 页目录表 的指针,通过CR3寄存器就可以得到一个表称为页目录表,页目录表内元素 称为 页目录项, 页目录项本质也是一个指针,指向一个 页表, 而页表内元素称为页表项,页表项内存在着 页基地址, 物理地址 = 页基地址(物理基地址) + 页内偏移(物理偏移地址)。
简单来说我们可以把 页目录表和页表想象成一个二维的数组。页目录表元素是页表(一维数组),页表元素则是页基地址。
我们只需要有两个元素(页目录表索引和页表索引)就可以得到一个物理(页)基地址,然后我们再将 页内偏移加上物理基地址,就得到了真正的物理地址了！而一个页在80x86中是4K大小(页基址 至 页基址 + 4K 为一页)。所以内存管理的页也是4K大小。
附图(寄存器数据) :
由图我门可以知道,页基地址(页帧),是4K对齐的(2^12 = 4K),也就是说页表项内只有12 - 31位是页基地址,其他的位是页属性,每次通过页表项计算物理地址只需要将 0 - 11位复位(0),即可。
对于页属性 : 表述这个页的权限之类的,因为有的页面是属于内核才能去使用的。更重要的一点是 : 这个页是否存在。
页目录和页表的表项格式:
如图所示 : 我们可以知道当 P位 被置位则表示页面存在,当 P位复位(为0) 则表示页面不存在,如若页面不存在,那么就会产生缺页中断,执行缺页中断处理程序。