Lab5: Preliminaries finishing (Alternatively, you can skip directly look at the experiment, watching the experiment remember to come back Kane)
1, under dc_shell to compile comprehensive optimization model design; compile_ultra to use the integrated optimization design under dc_shell -topo mode;
2, is integrated layered design: Architectural (level structure), Logicl (logic level), Gate (gate level)
3, each of the levels optimization strategy:
(. 1), Architectural (stage structure) comprising: a structural design choice, to optimize the data paths, shared (arithmetic circuit) subexpression, shared resources (where the arithmetic default resource sharing constraint-driven, variable is set to the hlo_resource_allocation area, such resource sharing strategy is the arithmetic constraint area (area optimization); hlo_resource_allocation variable to the DC none even disabled when integrated resource sharing, but this time may be specified in the RTL code resource sharing) , reordering operation symbol.
(2), Logicl (logic level): a functional circuit device represented in gtech performed Structuring (structure) and Flattening (flattening) optimization.
Wherein Structuring (structure) of a common strategy to optimize use (gate level) sub-expressions, optimization of speed and area, set_structure ture enable command.
Flattening (flattening) the combinational logic path optimization is reduced or after the first two, is about the expression of gates and written in a plurality of product, speed optimization, set_flatten ture -effort low (medium or high).
(3), Gate (gate-level) Optimization: DC mapped starting (delay optimization, design rules adjusted to the timing at the expense of design rules adjustment, area optimization) to complete the gate level circuits, e.g. mapping a combinational logic circuit is from the target library satisfying a timing combining unit area required to complete the design of combinational logic (which may include adjustment logic expressions and critical path dividing means); mapping sequence circuit is selected to meet the timing from the target library, the required timing unit area (usually complex) to complete the logic design;
4, other optimization cases: When a copying driver driving a plurality of registers and divides Register register bank is driven (lower dc_shell -topo use compile_ultra -timing);
When a module is called multiple times, the name of a unique (though with a module, but different names), corresponding to uniquify command.
5, the timing optimization methods: timing violations may be used when 25% of the cases:
(. 1), some compile_ultra switch options:
compile_ultra -scan -no_autoungroup -no_boundary_optimization -no_uniquify -area (Timing) _high_effort_script
corresponding respectively: to test the DFT editor, turn off the automatic cancellation division of functions, no boundary optimization is not the only name of a module to speed up the time patients with multiple calls to the module design, the area (timing) optimization.
(2), set compile_ultra_ungroup_dw ture # cancel all DesignWare level, comprehensive after boundary between each large block is cleared.
After a comprehensive set compile_auto_ungroup_delay_num_cells NUM # A large module is cleared and the boundary between the small module B is called A.
(3), to optimize the boundary: boundary some fixed pin or a fixed logic level (GND, VCC) are optimized.
(4), BRT techniques: (Behavioral ReTiming): includes gate-level netlist comprising register are optimize_registers, the combinational logic between the front and rear stage register is divided between the recombination sequence such that the register meet the requirements, or option added -retime migration between logical paths (adaptive retiming), such that the path does not meet timing requirements may be migrated logical path adjacent to meet up timing (timing devices typically by migration), set_dont_retime [XXX] ture can not migrate allow dc some devices; and pure combinational logic gate-level netlist pipeline_design (pipelining), when using this command will need to preset the registers in RTL. Not compile -scan -inc # compiler optimization only when the logic level gate-level optimization.
(Path group: combinations of a plurality of timing paths (register to register path control group due clk, clk default path group) path delays:. Cell-arcing time (cell delay + setup / hold time check time + cq ) + wiring delay (line load model calculation), and the path delay of the delay cell is the starting point and the rising edge (rising transition of the input signal) or the starting point is a falling edge (falling transition of the input signal) relevant (tphl, tplh ) .DC is to calculate the starting point for the implementation of report_timing rising edge delay and the falling edge delay calculation starting point and identify the critical path for each path in the group, the final report .DC display timing of each group is the default behavior for the same path group after the completion of the critical path optimization optimize fishes times the critical path (sub-critical paths), the critical path is never on time to optimize the critical path does not meet timing requirements, but sometimes we do not think is in the critical path optimization upon completion of the optimization of the critical time path, a path that can be customized or set group key range)
Custom path group: group_path -name XXX -from [XXX] -to [XXX], - from -to maximum priority, -from followed, -to minimum priority. Integrated DC do when each group independent optimization of each path group in the worst timing path. Optimization may also be provided weights (weight between the respective path group) and optimizing critical range (only path timing violations beyond this optimized) group_path -name XXX -from [XXX] -to [XXX] -critical critical num - weight weight num
Re-division module: automatic and manual partitioning division.
Lab5: experimental structure is as follows:
the top-level structure:
submodules structure:
parsing requirements and the corresponding test scripts:
. 1,
group_path -name CLK -critical 0.21 -weight. 5
group_path -name -from the INPUTS [all_inputs]
group_path -name OUTPUTS -to [all_output]
group_path -name COMBO -from [all_inputs] -to [all_output]
custom set of paths and path group weights clk highest weight (5).
2, 3 and 4 corresponding to the experimental requirements: INPUT sub-module structure to be protected, the need for sub-module PIPELINE BRT art optimize_registers, also need to be protected, so that the two sub-modules can not be broken.
set_ungroup [get_designs "the INPUT"] false
set_optimize_registers to true -design the PIPELINE
3、对应实验要求 5 和 6：子模块 PIPELINE 的输出寄存器不可以被流水线移动，子模块 I_DONT_PIPELINE 的寄存器也不可以被流水线移动。
set_dont_retime [get_cells I_MIDDLE/I_PIPELINE/z_reg*] true set_dont_retime [get_cells I_MIDDLE/I_DONT_PIPELINE] true
4、设置综合中时序优先：set_cost_priority -delay
5、验证：
①、查看时序路径组情况是否与上述分组一致：
report_path_group
②、查看子模块 PIPELINE 有没有进行optimize_registers:
get_attribute [get_designs “PIPELINE”] optimize_registers
③、查看 INPUT 的打散情况和该需要不被移动的单元或者模块的移动情况：
i、get_attribute [get_designs “INPUT”] ungroup
INPUT 模块没有被打散。
ii、get_attribute [get_cells I_MIDDLE/I_PIPELINE/z_reg*] dont_retime
所有的 z_reg*寄存器在 retiming 过程中没有被移动。
iii、get_attribute [get_cells I_MIDDLE/I_DONT_PIPELINE] dont_retime
模块 I_MIDDLE/I_DONT_PIPELINE 在 retiming 过程中没有被移动。
④、查看综合中是否是设置建立时间冲突的优先级高于 DRC 冲突 (Prioritize fixing of setup timing (delay) violations over DRC violations): get_attribute [get_designs “STOTO”] cost_priority
⑤、compile_ultra -retime -scan 之后查看没有被打散 ungroup 的模块：
report_hierarchy -noleaf
⑥、查看时序报告：
redirect -tee -file rt_compile_ultra.rpt {report_timing} 可以看到各个路径组分别的时序报告。
其中 clk 组中优化权重最高并且在 PIPELINE 加入 optimize_registers，不存在时序违规，slack为正值：
⑦、查看子模块 PIPELINE 进行 optimize_registers 之后被移动的寄存器： report_cell -nosplit I_MIDDLE/I_PIPELINE#查看例化名字对应的原模块的名字 report_cell -nosplit I_IN#查看例化名字对应的原模块的名字
或者：
get_cells -hier r_REGAfter _S * # optimize_registers been moved to register the name r_REG _S * (start_gui see a graphical interface, most of the register name to see I_MIDDLE / I_PIPELINE in)
estimate of register has been moved z1_reg and other registers.
-hier get_cells z_reg # verify whether the register is moved z_reg:
presence value, indicating z_reg not be moved.
-hier get_cells z1_reg whether the validation register # z1_reg been moved
no value exists, described retiming register is moved to z1_reg.
R_ -hier get_cells # view retiming process had been moved is not in the pipeline registers, retiming of the process is not being moved through the pipeline register is named R_
get_cells I_in / the _reg # Check module has not been moved through the INPUT register (start_gui difference comparison circuit diagram showing the name of the module before and after the INPT register)
before:
after:
In fact, no Lab6 hee hee
