STM32F103 the I2C learning record

26.3.1 Mode Selection

The peripherals can be in one of four modes

1) The slave transmit mode

2) The slave receive mode

3) The master transmission mode

4) The master receive mode

IIC protocol timing

MSB: Most Significant Bit (MSB)

Starting conditions: SCL is high state, SDA down from the high level

Stop conditions: SCL is high state, SDA pulled from low

Transmission of order data: first transmitting high

FIG I2C module

IIC can be seen that the module has:

1) data register, data shift register, a comparator, the PEC calculator

2) its own address register, dual address register, register the PEC

3) data control unit

4) clock control unit

5) The noise filter

26.3.3 I2C Master Mode

Desired master pattern sequence

1) I2C_CR2 configuration register to generate the proper timing

2) Configuration Control Register Clock

3) Configure the rise time register

4) configured to enable the peripheral register I2C_CR1

5) set the start bit I2C_CR1 register to generate a start condition

Peripheral input clock:

In sm mode, at least 2MHZ

In Fm mode, at least 4MHZ

When the main clock SCL

CCR bit SCL clock for generating high and low, respectively, starting from the generation of the rising and falling edges. When the SCL line extending from a device may, SCL input from the peripheral bus inspection at the end of the programmed time, generated when the rising edge.

If the SCL line is low, which means that a node is being stretched from the bus, the counter will stop the rise until the SCL line is detected to be high. This ensures minimum SCL clock high cycle parameters.

If the SCL line is high, the high level counter continues counting. If the SCL line is high, the high level counter continues counting.

In fact, the rising edge of the peripheral device from the peripheral device to generate SCL SCL rising edge detector feedback loop takes time, even if the clock is not extended from the device.

START condition

When the busy bit is cleared, the start bit is provided so that the interface generates a start condition, and switches to master mode.

In master mode, setting a start bit will cause the interface to generate restart condition at the end of the current byte transfer.

Once the starting conditions has been transmitted:

SB bit is set by hardware if the bit is set ITEVFEN, it will generate an interrupt.

26.3.6 SMBus

System Management Bus (SMBus) is a two-wire interface, through which various devices may communicate with each other, it may also communicate with the rest of the system.

它基于I2C操作原则。SMBus为系统和电源管理相关的任务提供了一个控制总线。

系统可以使用SMBus来在设备之间传递消息，而不是切换各个控制线路。

系统管理总线规范涉及三种类型的设备。

1）从设备是接收或响应命令的设备。

2）主设备是发出命令、生成时钟并终止传输的设备。

3）主机是为系统的CPU提供主接口的专用主机。主机必须是主从主机，并且必须支持SMBus主机通知协议。

系统中只允许一个主机。

SMBus与I2C之间的相同点

1）都是有两条线：时钟线和数据线+可选线

2）主从通信，主机提供时钟

3）多主能力

4）数据格式类似