2019-11-13 10:52:30
Chapter 3 - System Bus
• bus width: D xf (frequency), the unit is MBps- megabytes per second (where D is the width, in bytes B)
• transfer information according to different bus systems can be divided into a data bus address + control bus Bus +
• When the root is x address bus, a corresponding memory cell 2 20
example:
A and B are computer using a different frequency of the CPU chip, on-chip logic circuitry is identical
(1) If A machine CPU clocked at 8Mhz, B is a CPU clock cycles 12Mhz, the machine is A?
Clock cycle = 1 / frequency so the answer is 1 / (8x10 ^ 6) s = 0.125us
(2) When the average instruction execution speed A machine as 0.4MIPS, then the average machine instruction cycle is A?
The average instruction cycle x 1 = average velocity instruction execution so that the answer is 2.5us
The average instruction execution speed (3) B plane is?
A number of instruction cycles required to machine A: = A average machine instruction cycle / clock cycle = 20 clock cycles
ps: instruction cycle> machine cycles> clock cycles
Since the same logic circuit A, B, and B so that a machine instruction cycle is 20 clock cycles , the average instruction cycle B is 1 / (12x10 ^ 6) s multiplied by 20 = (5/3) 10 ^ -6s
And then to calculate the average instruction execution speed B of (2) of the formula 1 / ((5/3) 10 ^ -6s) = 0.6MIPS
• distinguish between baud rate and bit rate:
Binary digit bps, the transmission unit time: baud rate
Bit rate: bps, the binary bits of valid data per unit time of transmission (data bits included only)
The fourth chapter memory
• Memory Category:
Memory - main memory (RAM) - - - - - - - - - - - - - - - - the RAM (cleared off) + ROM: read-only memory
--- Flash
--- secondary memory (disk, tape, optical)
--- Cache
• In general: the larger memory capacity, slower
• chip capacity (bits) = 2 address line x data lines (number)
• 16Kx1 bit corresponding chip 2 ^ 14: 14 address lines a data line, wherein K is 2 ^ 10
• Connection of respect to the memory and cpu
example:
Known CPU has 16 address lines and 8 data lines prior 1K x 4 bit RAM, 4K x 8 bit RAM, 8K x 8 bit RAM, 2K x 8 bit ROM, 4K x 8 bit ROM, 8K x 8 bit ROM
If the main memory address space is allocated as follows:
6000H ~ 67FFH system program area
6800H ~ 6BFFH for the user program area
First: the system program ROM area should be composed, and the user program with the RAM area;
And then converted to hexadecimal:
System program area:
0110 0000 0000 0000
0110 0111 1111 1111
Subtraction of (011111111111) 2
1 11, application 11, 2K represented, seen from the meaning of problems memory word length is 8 bits, selecting a 2K x 8-bit RAM
User area:
0110 1000 0000 0000
0110 1011 1111 1111
Subtraction is 001111111111
1K x 8 should be chosen place;
In the absence of 1Kx8 bit select two 1K x 4 bit RAM
CPU line address assignment: A10 ~ A0 11 root connection (2Kx8 bit ROM) address lines
A9 ~ A0 10 root connecting two 1Kx4 bit RAM
ROM corresponding to the data lines D7-D0, RAM 2 corresponding to the slice data lines D7-D4, respectively, D3-D0;
• Refresh on dynamic RAM
Refresh associated with the row address
① centralized refresh: refresh will stop when reading and writing, will form a dead zone, affecting the efficient use of computer systems;
② dispersed refresh: no dead zone, but access cycle lengthened;
③ asynchronous refresh: dead zone is very short, and the use of the characteristics of 2ms refresh interval;
• Cache:
the cache hit rate and the cache capacity and block length of about (the longer the capacity, the higher the hit ratio cpu)
example:
Assuming that the CPU executes a certain program, a total of 2000 hits cache access times, access to the main memory 50 times. Known cache access cycle 50ns, main memory access cycle is 200ns. Seeking hits Cache- system main memory,
Efficiency and average access time.
(1) Cache hit rate
Hit rate = Total Hits / (cache hit count + Visits main memory) to access the Cache h
Therefore, the hit rate of 2000 / (2000 + 50) = 0.97
(2) Efficiency equation: cache hit access time is T C , access cache hit rate h, misses the main memory access time T m
tc / (h tc +（1-h） tm )
Known main memory access time is four times the cache access
Therefore, the main memory access efficiency cache- e = tc / (0.97t + (1-0.97) 2tc) = 91.7%
(3) the average access time is the formula: HT C + (. 1-H) T m
50ns x 0.97+(1-0.97)200ns = 54.5ns
• Cache- main memory address mapping
First and distinguish byte addressable by word addressing:
If the block length is 4 words, 32 bits of each word within a word block address is the number of bits:
Byte addressable :: 4 x 4B = 16B = 2 ^ 4B, total 4
By word addressing: (4 x 32) / 32 = 4 = 2 ^ 2, a total of 2
• Then the title according to most of the main memory capacity can be determined median total length
When the main memory capacity is 512Kx16 bit, Cache capacity 4096x16 bits block length of 4 x16-bit word, a word address memory access address.
Solution: the direct-mapped: cache block addresses and the number of blocks related (4096x 16) / (4x16) = 2 ^ 10, 10 bit
512Kx16 bit words total length of / 2 ^ 19 = 16-bit, 19-bit
If entitled: known main memory capacity of 512KB, cache capacity of 4KB, each word block is 16 words. Each 32-bit word
Solution: total length of 19 (512K = 2 ^ 19)
Direct mapping: cache block address cache block size / block size of 4KB / (4Bx16) = 64 = 2 ^ 6 total of 6, the block address word: 16x4B = 64B, 2 ^ 6, a total of six bits are allocated as follows: 19 -6-6; 6; 6
ps: recommendations for unspecified byte addressing process
If set associative mapping, cache block addresses based on direct mapping also divided on solving the "large ones"
By subtracting the total length of the full-associative address word block length of the block flag is the main memory word length;
• Below that constitute the mapping modes:
Direct mapping: main memory word block marked + + Cache block address within a block address word
Full associative mapping: main memory word within a word block flag block address +
Mapping contiguous group; + main memory word block flag set of markers within the block address word +
• Disk group disk 6, the outermost sides of the disk may be recorded, a storage area of 22cm internal diameter; outer diameter of 33cm, the track density of 40 / cm & lt, the inner density of 400 / cm & lt, speed of 3600 rev / min.
(1) the total number of available storage surface?
2x6 = 12 surface
(2) the total number of cylinders?
= The number of tracks recording surface, with an outer radius - inner radius = the effective storage area, a storage area of the effective track density x = the number of cylinders
Therefore 40 / cm x (33 / 2-22 / 2) = 220 plane
(3) The total disk storage capacity?
The inner circumference track = 3.14x22 = 69.08cm
Each channel of information bit 400 x 69.08 = 27632 = 3454B
Each side channel information for each information amount x = number of tracks = 3454B x 220 Road
The total capacity of the disk plane x = number of stored information per side = 2x 6 x 3454 x 220 = 7.24MB
(4) The data transfer rate?
Dr = nN = x speed = 60 rpm capacity of a single track / s x 3454B