Almost thought he would P3 dove out of blog, but through the efforts is still made out testing requirements under class CPU. Meng as a new engineering capabilities are new to training courses, not lack the courage to do it all over (the first edition of ten hours made an end, plus a bunch of bug can not expand very well), take over only the first pass, can really appreciate what problems encountered, will understand the essence of high boss courseware, in order to better wiring in the second edition, naming, and the rational use of tunnel. In order to write lab reports, put up on the blog, and then modify the blog based on a test report.
The contents of the following: first build process, pits error-prone points and trick summary
:( build process is similar to the narrative of this paragraph, the equivalent of a diary)
After reading the first few pages that required!
At that time not learn to theory, to build a little individual components. GRF Needless to say, certainly with the setting up of P0, CPU can start over, but the GRF to be multiplexed. Note GRF have Reset, Reset total press time PC, DM, GRF must return to the original state (teaching assistant at the forum said) . IFU (instruction fetch unit) I split into two sub-circuits PC with IM. Note PC has the Reset, IM using a ROM, as long as these requirements should be carefully read no problem. 32bitALU nothing special, but consider that in order to facilitate future extensions (such as adding operation instructions), I spent three ALUOp, that supports 8 ALU operation, only unsigned or subtraction, and computation. For DM (Jiaosha I do not know, because it is memory), pay attention to the input address is 5 (* 32 requires 32bit), attention has reset, attention MemWrite role is to write data to the time 1 , data from the outside in memory, rather than writing out of memory! At this point, we talked about class foundation was set for the element. But I recommend you to build a universal splitter , its top a long way:
Function we can look too literally, the top layer wiring after he had also imagine everyone will be very simple, the signal needs only one line will be able to lead out.
Here starts from a data connection path, a high strength engineering approaches push the boss here! Rely on their own textbook or teacher (my theory class teacher is not the boss) courseware for 7 instruction the CPU will not bother, but more instruction after the engineering method would do well to let us add command and add elements. I was even beginning to start addu passage, law books or even specific courseware has been very clear, not described in detail. Even then lw and sw, followed up on lui instruction. Here I have no instruction into ALU lui, but separate at the top which added a 16-bit logical shift left shifter, and the results of the ALU and the result made a multiplexer, the selection signal is called AorS_sel, of course, the selected results inevitably and finally read out data from memory to do another multiplexer, the signal is called MemtoReg. in addition, when I type these instructions, be sure to read MIPS manual to see in the end is 0 or extended sign extension or need shifted left two bits and the like. Finally, I added BEQ, in order that the chaos line, where I IFU PC + 4 + offset calculated at the tunnel with simplified wiring.
Data path is not difficult to draw, the controller needs to think about, and a good look-up table, create table. I put the controller into two parts, a look OpCode part, the other is the need for a comprehensive first part ALUOp signal is given and Func signal to generate ALUcontrol signal (the number of bits to look at yourself). It is the two-part structure or gate arrays, and the first portion thereof is negated OpCode six battlefield, and the second portion is inverted and Func ALUOp its negated battlefield. To connect, we need to check the manual mips, connected to a gate array, and then re-table joins or gate array. The order made table below briefly about. First moved here tutorial
I began as an iron Han Han, fill in the table sideways, which is filling the order of a nuisance, because every fill line, you need to want the data path for all instructions again, want to get hurt skull. The second building when I consider bristling fill in a form , fill each one just need to access the instruction to go again, thinking the amount is reduced from O (n ^ 2) to O (n), is not easy wrong. Determine the data in the table is determined by their design, the data can not be given in the tutorial agree. Further, for the R type instruction, all of the R type instruction in the synthesis of a gate array and gate line, called R IF, as do the final R type instruction, or depending Func, so that the controller in the first part of all R-type instruction all can be classified as a class. IF the results of R, R-type instruction considering the inevitable regfile written, it is connected to and RegWrite. As in the first portion ALUOP, where their value is dependent on the design of the ALU predetermined A rule 000 for the adder, subtracter 001, or 010 to 011 for the comparison, 100 is a field depending Func. The general idea of a first portion of the controller has finished, consider the following idea to build the second portion of the controller. The first time I set up the second part, because of ill-considered + courseware boss did not look high, a serious flaw, as they do wrong then I will discuss. One right (should correct it, so the class will know) the program is still used with or gate array. With gate arrays or did not understand? For the R type instruction, consider an example : Addu example, it is Func 100 001, 100 needs to take effect at ALUOP, therefore, we take this nine lines corresponding to (1 take the original signal, taken inverted after 0 signal) are connected to the addu the job and on the door. Figure:
In this case, if the signal is not ALUOp 100, then it is not described R type instruction, Addu naturally can not take effect. I believe that with this example, a better understanding of the part or the door. Because Xueyibujing, I will not take the very beginning here, in a reminder roommate found and the first part of the controller is exactly the same (stupid not mind mastery ah) With this example, I believe the analogy of other cases also easy to implement. But really speaking, the second part of my bad controller design, use a constant zero to assist, if the add instruction, I need to get rid of 0, and think about how to expand so that the signal will not be chaos. Here is mine, do not know can not be killed himself Thursday. After the two parts are completed, the controller will take over. I use all the control signals tunnel connected to everywhere, so feel more readable.
In this way, CPU will take over, when it is born so long:
Too difficult to see, but if you take the words as I write thinking, the second time is this:
With the addition of the name of the signal, and deliberately to increase the size of key components, and finally looks like a CPU of the (not too strong test, do not know if I have a problem)
It is 2:47, just found a weak test results finally came out, WA third point. Discussion read, find their MemAddr take wrong (32 to 5 encapsulated inside the wrong figure). In order to ensure a multiple of 4, similar to the address-PC part, should take place 2-6 instead of 0-4 ! ! ! Universal Forum! ! ! Actually, this is one of my knowledge blind spot: Modern computer byte addressing, if you write sw $ s1,20 ($ s2), it is the presence of the first five words (32-bit machine). The DM is an address in a word, it is divided by 4, that is to take place 2-6! !
About the test: http: //shell-storm.org/online/Online-Assembler-and-Disassembler/ disassemble transformed the site, choose mips, bigendian, then disassemble the line.
After a weak measurement, then also need to focus on visual check branch and jump instructions and instructions related to negative, the current thought up the other (too sleepy), thought to fix it!