LEF file layout is based on the file format of cell geometry repository use, the following is part of a LEF file, the right is the explanation for him. Place and route tools will determine how the layout based on the information LEF file, how to walk the line, how to generate vias.
VERSION 5.5; Imprint
NAMESCASESITIVE ON; LEF format distinguished sensitive.
BUSBITCHARS "<>"; setting defines bus identifier, the port name of X <1>, X <2>, ... X <n> be regarded as bus
UNITS
DATABASE MICRONS 100; 1 [mu] m defined set divided into 100 unit, is the value per unit length.
END UNITS
LAYER metal1 set defining layer is a metal layer 1, while the following is a definition of a metal layer 1 disposed details.
TYPE ROUTING; defined for routing metal1
WIDTH 0.10; defines a metal as a wiring metal layer, a line width of 0.1 um default
SPACING 0.30; 1 traces defined metal layer pitch 0.3um
1.2 the PITCH; distance defining a metal layer to the through hole is 1.2
DIRECTION HORIZONTAL; 1 metal wiring layer traces a horizontal direction.
CAPACITANCE CPERSQDIST 0.000140; provided that each define a square (1x1um) the size of the capacitor.
RESISTANCE RPERSQ 0.04; provided a sheet resistance of each metal.
END metal1
LAYER via
The TYPE CUT; is defined as CUT via the type of layout, i.e. Metal1 through hole and Metal2
END via
This setting defines LAYER metal2 metal 2, metal 1 is provided above the like.
TYPE ROUTING ;
WIDTH 0.30 ;
SPACING 0.30 ;
PITCH 1.20 ;
DIRECTION VERTICAL; provided the difference between the metal layer 1, a direction perpendicular alignment.
CAPACITANCE CPERSQDIST 0.000120 ;
RESISTANCE RPERSQ 0.020000 ;
END metal2
VIA M1_POLY1 DEFAULE setting defines how the through hole is generated, the generated here between metal vias and the poly1 by default. Vias generated here is generated when the upper and lower layers are default width, when the width of the upper and lower layers than the default, there is another rule definition.
LAYER poly1;
RECT -0.30 -0.30 0.3 0.3; set defining the shape of Poly1 (polycrystal) is.
LAYER cont;
RECT -0.15 -0.15 0.15 0.15; CONT disposed defined shape (contact hole) is.
LAYER metal1;
RECT -0.3 -0.3 -0.3 0.3; set defining the shape of metal1
END M1_POLY1
VIA M2_M1 DEFAULT the through hole is provided between the metal1 and metal2 define default. Similar to the above through hole is provided.
LAYER metal1 ;
RECT -0.30 -0.30 0.30 0.30 ;
LAYER via ;
RECT -0.15 -0.15 0.15 0.15 ;
LAYER metal2 ;
RECT -0.30 -0.30 0.30 0.30 ;
END M2_M1
VIA M3_M2 DEFAULT between the through hole and defines metal2 metal3.
LAYER metal2 ;
RECT -0.30 -0.30 0.30 0.30 ;
LAYER via2 ;
RECT -0.15 -0.15 0.15 0.15 ;
LAYER metal3 ;
RECT -0.30 -0.30 0.30 0.30 ;
END M3_M2
VIARULE VIAGEN21 GENERATE through holes previously provided in different, provided that the rules define the through holes generated in the non-default .
LAYER metal1 ;
DIRECTION HORIZONTAL ;
OVERHANG 0.3 ;
metaloverhang 0.0;
LAYER metal2 ;
DIRECTION VERTICAL ;
OVERHANG 0.3 ;
metaloverhang 0.0;
LAYER via ;
RECT -0.15 -0.15 0.15 0.15 ;
SPACING 0.6 BY 0.6 ;
END VIAGEN21
SITE standard defines various setting of the site, site of standard cells as defined herein.
SYMMETRY y ;
CLASS core ;
SIZE 1.20 BY 10.80 ;
END standard
The site defined set SITE IO IO unit.
SYMMETRY y ;
CLASS pad ;
SIZE 21.05 BY 70.80 ;
END IO
SITE corner of the site pad provided on the chip define four corners.
CLASS pad ;
SIZE 70.80 BY 70.80 ;
SYMMETRY y r90 ;
END corner
This setting SITE SBlockSite hard core unit block defined the same site, for the block, such as RAM / ROM, HardIP.
CLASS core ;
SIZE 1.00 BY 1.00 ;
END SBlockSite
LEF defined above various layout rules, tool layout according to these rules. LEF above is the layout tool data using a similar process LEF file properties.
The following definitions of the various different cell geometry, there is provided a layout tool.
LEF MACRO AOI21_B the information provided in the definition unit AOI21_B.
ORIGIN 0.00 0.00; setting defines the origin of the coordinate.
SIZE 6.00 BY 10.80; setting defines the cell size, in units of um
A SYMMETRY xy; setting defines the tool may rotate the display unit in the xy direction.
SITE Standard; the definitions set standard site, the setting indicates that the unit is a standard cell type, as well as other types of the IO, as is SITE IO.
CLASS CORE; provided that the cell is defined in the kernel rather than the chip may be placed in a position of IO.
PIN vdd! Name setting defines the power supply pin vdd! .
USE POWER; setting defines the VDD! For power.
DIRECTION INPUT; setting defines the VDD! Is the input PIN feet.
SHAPE FEEDTHRU ;
PORT
LAYER metal1; vdd this setting defines the unit! shape. .
RECT 0.00 9.15 6.00 10.65; This setting defines vdd! A metal layer RECT rectangular shape parameters.
END
END vdd!
PIN gnd! This setting defines the name of the ground pin gnd! .
USE GROUND; GND defines the set! For the ground.
DIRECTION INPUT; GND defines the set! Is the input PIN feet.
SHAPE ABUTMENT ;
PORT
LAYER metal1 ;
RECT 0.00 0.15 6.00 1.65; GND defines the set! A metal layer RECT rectangular shape parameters.
END
END gnd!
The definition of the Y provided PIN PIN pins Y.
DIRECTION OUTPUT; Y is defined setting the output terminal.
PORT
LAYER metal1 ;
RECT 4.12 2.32 4.28 2.48; this setting defines a Y shape in a layer of metal.
RECT 5.32 8.32 5.48 8.48 ;
RECT 5.32 7.12 5.48 7.28 ;
RECT 5.29 5.89 5.51 6.11 ;
RECT 5.29 4.69 5.51 4.91 ;
RECT 5.29 3.49 5.51 3.71 ;
LAYER cont ;
RECT 4.05 3.15 4.35 3.45 ;
RECT 4.05 2.25 4.35 2.55 ;
RECT 5.25 8.10 5.55 8.40 ;
RECT 5.25 7.20 5.55 7.50 ;
END
END Y
This parameter set defines OBStruct OBS blocked, i.e., the wiring area can not be defined below, (here metal1).
LAYER metal1 ;
RECT 5.09 1.95 5.85 2.71 ;
RECT 5.09 3.29 5.85 3.91 ;
RECT 5.09 4.49 5.85 5.11 ;
RECT 5.09 5.69 5.85 6.31 ;
RECT 5.09 6.89 5.85 7.51 ;
LAYER via; setting defines the layout tool is not punctured place.
RECT 5.28 7.08 5.52 7.32 ;
RECT 5.28 8.28 5.52 8.52 ;
RECT 4.08 2.28 4.32 2.52 ;
END
END AOI21_B
END LIBRARY
1， SITE
SITE standard setting defines the site.
SYMMETRY y ;
CLASS core ;
SIZE 1.20 BY 10.80 ;
END standard
site layout tool identification unit is the smallest unit of geometry, a site may have several design, site Standard refers to a standard cell site, the IO site refers to the site IO pad. Generally, the height of the cell is constant, equal to the height of the site, the width of the cell site is an integer multiple.
2， Via rule
Rules through a pore, when wiring lines of different layers when the connection requires open holes, different situations require different through the generation of holes, the through-hole what generated through a pore is determined by rules within the LEF.
3， pitch
LEF pitch is an important concept, which defines the wiring pitch of the future, its wiring has a great effect
influences. pitch spacing is the same layer of metal, a grid layout is the wiring, a wiring which is the minimum grid pitch 1, as shown below.
Grid along the signal line go, pitch greater than or equal line to via spacing, i.e. to ensure alignment on a lattice point, the lattice points adjacent perforated hole pitch line spacing does not violate the rules. In the multilayer wiring, or maintaining the same general definition of a simple relationship Pitch layers, such as 1: 2, thus ensuring good and routing. pitch size must be carefully considered.
4， abstract
A complete map of cell contains information on all the layers, but in place and route tool use, do not need so much information, place and route tools just know where the pin is, what can not wiring, and so less information on it , thus reducing the amount of data to improve the processing speed.
Shown below is a cell layout (layout) and its graphical depiction of LEF. Abstract layout with the cell information to the wiring.
There are some specialized tools for the complete layout cell turn into abstract, such as the abstract generator cadence.