Back-end terminology: In back-end design, what do GDSLL, LEF, DEF, SDF, SPEF, and SDC mean? In front-end and mid-end processes, what do SVF and SAIF mean?
1. GDSII: describes the layout level, shape, position, geometry, topological relationship and other information. It is a text for circuit designers and foundries to exchange information. It can also be used for parasitic parameter extraction, power consumption analysis, and voltage drop analysis.
2. LEF: library exchange format There are two types of physical library information used for layout and routing. A tech lef contains technical information (physical properties, design rules, antenna effects) of the process. One is that cell lef contains the information of each cell in the cell library (one part is to use the site statement to define the smallest unit of the layout, and the other is to use the MACRO statement to describe the cell properties and geometric shape).
Below is an example of a LEF file. MACRO is a keyword defined by a unit, and each MACRO represents a unit. CLASS core indicates that the unit is used in the core area of the chip. SIZE determines the size of the unit. For example, 5.04 represents the height of the unit. When doing the unit power supply route later, you can see that their width is this value, which will be defined later. Pins A, B, Y, VDD, VSS.
3. DEF: designexchange format, the file format used to describe the physical design information of the circuit. It not only contains the connection relationship of the circuit but also describes the specific physical information of the unit and interconnection after the circuit layout and wiring.
4. SDF: standard delay format describes the delay data of units and interconnection lines after circuit layout and wiring. Since the delay information at this time is closest to the real situation of the circuit, the main function of the file is to back annotation to the front-end simulation tool to verify the timing function of the circuit gate-level netlist generated after layout and routing.
5. SPEF: standard parasitic exchange format chip parasitic parameter file, which includes RC extraction results (SPF), as well as inductance L and conversion time slew, for SI, STA analysis;
6. SDC: The synopsysdesign constraints design constraint file is used for timing, area, and power consumption constraints of logic synthesis and physical implementation, so that the chip meets the specifications required by the design.
7. SVF: It is the output file of the DC tool, which is used for Formality check. The file only needs to record various optimizations of DC to RTL, register name changes, and so on.
8. SAIF: used for power analysis and IR drop analysis. It mainly describes the flip rate (toggle rate) and static probability (static probability) of each net and each CELL pin in the design