Interrupt function is to suspend execution of the current program, and turn to execute another program. Cpu instruction within the interrupt is generated by the execution of the
system's built-in interrupt
Divide error, such as division instruction execution div 0 overflow resulting
single step an
execution instruction 4 into
execution command N int
Interrupt handler
The interrupt handler is cpu after receiving an interrupt message, the need to interrupt the information is processed, the information is used to interrupt the process known as the interrupt handler
Interrupt vector table
Address CPU 8-bit interrupt type code through the interrupt find the entry address of the appropriate interrupt handler to the scale, the interrupt vector table is a list of interrupt vector, that is, the interrupt handler entry of
the interrupt is the vector table storage location for the 8086, specifies the interrupt vector table in memory address 0, from memory 0000: 0000-0000: 1024 cells 03FF is stored in the interrupt vector table,
Interrupting the process
IP will point to the interrupt handler entrance, CPU starts executing an interrupt handler: CPU interrupt after receiving the information, the information is processed to interrupt, the interrupt process is first initiated, the hardware interrupt process is completed, CS
after receipt of interrupt information below is cpu , triggered interrupt process
Interrupt type code acquired from the information in the interrupt
flag register stack
disposed IF and TF flags register is zero
the content of the stack value CS
IP contents of the stack
in the interrupt vector in the interrupt handler obtained CS and IP
Use assembly language, he said:
pushf
TF = 0,IF = 0
push CS
push IP
(IP) = (N*4),(cs) = (N*4)+2
Interrupt handler and instructions iret
Process interrupt handler is
Save registers used in
interrupt
restore registers used in
the return instruction with iret
iret assembler instructions as described
pop Ip
pop CS
popf
Respond to special circumstances interrupted
Generally, cpu after the execution of the current instruction, if the interrupt information is detected, corresponding to the interrupt, the interrupt process is triggered, in some cases, cpu current instruction to complete, even if an interrupt occurs, it will not corresponding, for example,
after executing provided ss instruction register after the data transfer, even if an interrupt occurs, CPU is not appropriate, because this is ss: sp points to the top joint. And they should be continuous to complete, when ss After setting, if the corresponding interrupt flag register push, push but where there is a problem, because the value is not set ip. Therefore, after the value of the cpu of ss been performed, not the corresponding interrupt information, the value of the continuous need ip and ss, and ss is provided on the front, sp is provided on the back
mov ax,1000h
mov ss,ax
mov sp,0
The following settings on this error
mov ax,1000h
mov ss,ax
add ax,10
mov sp,0
Single-step interrupt
Substantially, cpu after executing one instruction, if it is detected TF flag register bit is 1, the single-step interrupt is generated, triggered interrupt process, single-step interrupt is an interrupt type code,