# 2019-2020-1 20,175,333 Caoya Kun "Information security system design basis" fourth week of learning summary

2019-2020-1 20,175,333 Caoya Kun "Information security system design basis" fourth week of learning summary

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• 1. pipelined processors:
  the execution of each instruction is broken down into five steps, each step processed by a separate piece of hardware, or stage. Step instructions by the pipeline stages, and each clock cycle there is a new instruction enters the pipeline. The processor may therefore perform the different stages of five instructions simultaneously.
• 2. programmer-visible state:
  Y86 each instruction in the program will read or modify some portions of the processor state. This is called a programmer-visible state.
• 3.Stat
  the last part of the program status is status code Stat, which indicates the overall status of program execution; it indicates normal operation or there is some kind of anomaly.
• 4.Y86
  a simple subset can be called IA32 instruction set instruction set; includes only four-byte integer operations, fewer addressing modes. Instruction bytes code length ranging from 1--6.
  Instructions regarding the structure, the first byte of each instruction indicating the type of instruction; This byte is divided into two parts, each four: 4 bits are the code portion (0--0xB), the fourth functional section. Here add some abbreviations: immediate (i), the register (r), the memory (m). Additional instruction register indicator byte followed by a data source (if it is immediate, this provided a 0xF), the destination register / base register. Some instructions often require additional four-byte number, using the little-endian (reverse) encodes
• 5.stat code may reflect different values ​​of state of the machine -
• AOK: normal operation (other than any state such that the processor will stop executing instructions)
• HLT: processor executing a halt instruction
• ADR: encountered an illegal address 2015/10/14 17:16:25
• INS: encountered an illegal instruction
• 6. It should be specified in the command code or data on what position the like. Wherein, in. The beginning of the assembler commands that tell the assembler to adjust the address to generate code or some data are inserted there.
• 7. YIS simulator simulates execution instruction Y86 machine code program without any attempt to simulate the behavior of a particular processor implementation.
• 8.pushl will stack pointer by 4, and a register value written to the memory. Thus, the results of pushl% esp popl% esp and is not fixed.
• 9. The logic gate is a basic computing element of the digital circuit. Always active logic gate, a gate input once changed, in a very short period of time, the output will change accordingly.
• 10. The combination of a lot of logic gates into one network, can build calculation block, called a combining circuit. Limit:
  the outputs of two or more logic gates not connected together;
  the acyclic network must
• 11. The multiplexing circuit (MUX): The value of the input control signal, selects one of a set of different data signals.
• 12. Some description about HCL
  HCL all word-level signals are declared in an int;
  painting stage circuit, when the word, with the middle line represents the thickness of each bit line carries words, a dotted line Boolean signal results
  in the HCL, represented by default (i.e. when all the conditions are not selected) with a general
• 13. The arithmetic / logic unit (ALU):
  The setting control input (0,1,2,3), a data input circuit will perform different arithmetic or logic operations (+, -, &, ^).
• 14. The timing circuit
  has a state and this state is calculated in system
• 15. A random access memory & clock register
  clock single bit register or memory word. The clock signal control input value register is loaded
  a random access memory storing a plurality of words selected by the read address or the write word which
• 16.Y86 order to achieve inseparable SEQ processor (sequential processor).
  An operation instruction processing organized into a special sequence of stages; may be designed to take advantage of hardware of a processor.
• 17. The processing operation stages -
  fetch: reading instruction bytes from the register, the address for the program counter value. Calculating the next instruction address is equal to the PC value plus the length of the instruction has been taken
  decoded: read up to two operands from the register file
  to execute: performing effective address specified ALU operations, reference is to modify the stack pointer or
  memory access : writing data to memory or reading data from the memory
  write-back: two write results to the register file
  update PC: PC set to the address of the next instruction
• 18. With regard to the processing of step number command
  processing rrmovl irmovl similar instruction, but since the instruction format is long, the program counter 6 to add
  instructions to the call and ret similar before and popl pushl. For instructions call, we want to valP address is pushed onto the stack from the instruction after the call in the PC update stage, the PC is set to valC, is calling destination
• 19.SEQ timing (gradual deepening)
  to control the timing of activities in the processor, the memory and registers only the clock control
  in addition to the instruction memory read command and therefore can be seen as a logical combination other than the remaining program counter, a condition code registers, data memory and register file needs to be controlled by a clock signal (control sequence)
  in each clock cycle, the program counter is loaded new instruction address; only perform integer arithmetic instruction, the condition code register will be loaded. Only perform rmmovl, pushl, call, will write data memory.
  Y86 nature of the instruction set to follow such an organizing principle: the processor never needed in order to complete execution of an instruction to read and updated by the instruction of state [how to understand? In other words, processors, "handling" of the directive, if there is some mechanism that can change the state; then execute the instruction after then it must first change state. This ensures that the timing of the operation (to prevent reverse execute each instruction)]
• 20.SEQ achieve phase
  fetch stage includes an instruction memory cells. A 6 bytes read from memory. The first byte is divided ocode, ifun. The value icode calculated: instrvalid (found invalid instructions), needregids, need_valC. instrvalid and imemerror in phase is used to generate memory access status code.
  In SEQ decode and write back stage requires access to the register file. Register file has four ports, which supports two simultaneous read and write two; each port is an address and data connections. If the value of 0xf special identifier on an address port, indicate that no register is accessed.
  Execution stage includes an arithmetic / logic unit (ALU). This revolutionary alufun signal setting unit performs ADD, SUB, AND, XOR operation on input aluA and aluB. ALU output is valE signal. Further comprising a condition code register. Each run, the ALU will generate the condition code associated with the three signals - zero symbols, overflow. Set_cc used to control whether the condition code register should be updated.
  Fetch stage. Two control block generating the memory address and the memory value of input data; the other two blocks should be performed to generate control signal indicates a read or write operation.