A system bus timing chart
Second, analysis
The first clock cycle starts, the system address bus an address memory space required is given access.
After Tacs time, given a corresponding chip select signal, and latches the current address information on the address lines.
After another Tcso time, the processor gives the current operation is a read (nOE low) or write (new low).
Tacc time within the data ready to put on the bus,
Tacc after time (and see nWAIT signal, this will be extended to low bus operation), nOE pulled, the data line data latch.
Such a bus operation basically completed.