https://mp.weixin.qq.com/s/82iLT-fmDg9Comp2p9bxKg
Brief realization of RegisterCrossing.
1. BusyRegisterCrossing
Simple control state machine, can initiate a request for controlling whether or not, i.e., whether there is a request being processed:
1) I
Control interface as shown below:
a. master_request_valid/master_request_ready
It indicates whether or not an upstream initiation request (valid), the downstream receiver is ready (ready).
b. master_response_valid/master_response_ready
Indicating whether or not response information (valid), is ready to receive the upstream (ready) response message.
c. crossing_request_valid/crossing_request_ready
It represents a request sent across clock to structure (valid), and passed through the downstream cross-over structures clock signal is ready (ready) to receive the.
2) busy
It indicates whether a request is being processed, at this time may not receive new request:
3) bypass
Loopback is equivalent to, if the bypass is true, then the request to transfer across clock structure, but directly returns a response message to the upstream:
2. RegisterCrossingAssertion
This assertion by the conditions as follows:
. A io.master_bypass: i.e. upstream of claim bypassed across clock structure, direct reply message in response, the state need not be concerned downstream;
.! B up: Downstream not up, then it will not use cross-clock structure;
.! C io.slave_reset: downstream is not reset, then the clock can be used normally span structure;
3. RegisterWriteIO
Write register interfaces:
. A request: write requests valid / ready control interface;
. B gen: data to be written;
. C response: a write request response message valid / ready control interface;
. D Bool (): a response message;
4. RegisterWriteCrossingIO
增加了时钟和复位信号的跨时钟写寄存器接口：
a. master是指跨时钟结构上游，slave是指跨时钟结构下游；
b. master_clock/master_reset：主时钟和复位信号；
c. master_bypass：是否绕过跨时钟结构；
d. master_port：写接口，包括valid/ready控制及数据；
e. slave_clock/slave_reset：从时钟和复位信号；
f. slave_register：跨越时钟过来的写的数据；
g. slave_valid：slave_register中的内容是否合法；
5. RegisterWriteCrossing
跨时钟域写寄存器模块：
分为三个主要部分：
a. io：输入输出接口；
b. control：控制模块；
c. crossing：跨时钟模块；
1) 连接时钟和复位信号
2) 连接control模块
3) crossing上游连接
4) crossing下游连接
5) assert
6. RegisterReadIO
读寄存器接口：
a. request：请求控制接口；
b. response：响应消息控制及数据接口；
7. RegisterReadCrossingIO
加入时钟和复位信号的跨时钟读寄存器接口：
8. RegisterReadCrossing
跨时钟域读寄存器模块：
9. AsyncRWSlaveRegField
用于生成异步读写的逻辑和寄存器域：
1) 参数
2) 异步复位寄存器
3) 跨时钟写模块
4) 跨时钟数据写入寄存器
5) 跨时钟读模块
6) 从寄存器跨时钟读取
7) 返回参数
a. async_slave_reg.io.q：寄存器中存储的数据；
b. RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port, desc)：使用跨时钟读写模块的寄存器域；