https://mp.weixin.qq.com/s/uGxn-Xec0LkwdaSsCtQBvw
Briefly introduce the realization of Periphery.
1. ExportDebugDMI/ExportDebugJTAG
These are two parameters used for parameter search:
ExportDebugDMI means export DMI interface;
ExportDebugJTAG means export JTAG interface;
2. DebugIO
Define the system debugging module interface:
Among them: only one of clockeddmi and systemjtag exists:
3. HasPeripheryDebug
HasPeripheryDebug is a trait. Introducing the trait adds a debugging module:
1) debug
Generate a debug module:
Connect it to cbus:
cbus is the peripheral control bus:
cbus.coupleTo uses cbus.outwardNode as the upstream node, connects to the TLFragmenter node, and then connects to the debug.node node:
debug.node Immediately dmInner.tlNode:
The core accesses the address space such as ROMBASE through this connection, the schematic diagram is as follows:
2) debugCustomXbar
Used to connect custom sink / source nodes:
The schematic diagram is as follows:
Currently debugCustomXbar is not connected to the upstream node.
3) sb2tl
Connect sb2tl.node to fbus:
The schematic diagram is as follows:
4) getOMDebugModule
Used to obtain the description information of the debugging device:
4. HasPeripheryDebugModuleImp
It is used to realize the interface connection logic with the debugging module. According to the type of interface to be exported, there are two cases:
1) Export DMI interface
Directly export DMI interface, DTM is realized by external:
The schematic diagram is as follows:
2) Export JTAG interface
Introduce a DTM module and connect directly with JTAG interface:
Create a DTM module in instantiateJtagDTM and connect it with the debugging module:
The schematic diagram is as follows:
3) Other connections
Connect the ndreset / dmactive / debugUnavail signal:
The schematic diagram is as follows:
5. SimDTM
If the exported DMI interface, use SimDTM module to simulate a DTM module and connect it with the DMI interface:
6. SimJTAG
If the exported is a JTAG interface, use SimJTAG to simulate a JTAG interface.
1) me
Define the IO interface of SimJTAG module:
Among them: jtag is the standard JTAG interface:
2) connect
Connect the IO interface of SimJTAG with the debug interface of the system:
The main one is to connect the jtag interface, clock and reset signal:
Note: The tb in tbclock / tbreset should be the meaning of testbench.
7. Debug
The Debug object is used to assist in connecting the debugging module, or to close the debugging module:
1) Connect the debug module
According to the two different interfaces exported, different connection methods are called:
Called in TestHarness:
2) Close the debug module
If you do not need to debug the module, you can choose to turn it off:
8. Overall structure diagram
The overall structure diagram of the debugging module part in BaseSubSystem is as follows (you can open the picture to view separately):
Reference link: https://docs.qq.com/pdf/DUXVXcG54S3RHZExV