. 1 Module1 RGB_init ( 2 // system input signal (clock reset +) . 3 INPUT cmos_clk_i, // module control clock . 4 INPUT rst_n_i, // the system reset signal . 5 // OV5640 output signal (from 5640 input to the FPGA) . 6 INPUT cmos_pclk_i, // camera clock . 7 INPUT cmos_href_i, // the frame sync signal output lines . 8 INPUT cmos_vsync_i, // vertical sync signal . 9 INPUT [ . 7 : 0 ] cmos_data_i, // pixel data 10 //The output signal of the module . 11 Output clk_ce, // camera frame data output / capture enable signal (12Mhz), understood that this is the most difficult signal 12 is Output de_o, // the data valid signal 13 is Output [ 23 is : 0 ] rgb_o, / / 24bit pixel data output 14 output vs_o, // vertical sync signal output 15 output hs_o, // the line synchronizing signal output 16 // pixel clock output channel 5640 module . 17 output cmos_xclk 18 is ); . 19 20 is // to maintain system stability, it is necessary to discard a portion of the pre-frame image is selected here discard 15, choose, there are 10 to 21 Parameter [ . 3 : 0 ] = CMOS_FRAME_WAITCNT 15 ; 22 is 23 is ASSIGN cmos_xclk = cmos_clk_i; // XCLK as the clock driver 5640, of 24 / 25Mhz 24 25 // in the handling of a reset signal m with passengers, the reset signal delayed 5 clock, the delay may not seem to be viewed in the subroutine 2 26 is // think process reset signal to the reset signal to maintain a full cycle of signal 27 REG [ . 4 : 0 ] = rst_n_reg . 5 ' D0; 28 Always @ ( posedge cmos_clk_i) // synchronized input clock to FPGA 29 the begin 30 rst_n_reg <rst_n_reg = {[ . 3: 0 ], rst_n_i}; 31 is End 32 33 is REG cmos_href_r = . 1 ' B0; // the cache line synchronizing signal 34 is REG [ . 1 : 0 ] cmos_vsync_r; // the field synchronizing signal buffer 35 REG [ . 7 : 0 ] cmos_data_r; // the FPGA 5640 is output to the data register, because the output is a process 16bit, the input signal is two cycles of treatment stitching 36 // in the line and field synchronizing signals cache, a data input buffer 37 Always @ ( posedge cmos_pclk_i) 38 is the begin 39 cmos_vsync_r <= cmos_vsync_i; 40 cmos_href_r <= cmos_href_i; 41 is cmos_data_r <= cmos_data_i; 42 is End 43 is 44 is // for determining a start & end data, while the frame counts for the field synchronization signal register 45 REG [ . 1 : 0 ] cmos_vsync_d; 46 is Always @ ( posedge cmos_pclk_i) // synchronization with the output clock 5640 47 the begin 48 cmos_vsync_d <cmos_vsync_d = {[ 0 ], cmos_vsync_r}; 49 end 50 // field start and end signal 51 is Wire vs_start; 52 is ASSIGN ! vs_start = (cmos_vsync_d [1])&(cmos_vsync_d[0]); //posedge mark the action 53 wire vs_end; 54 assign vs_end=(cmos_vsync_d[1])&(!cmos_vsync_d[0]); 55 56 //行同步信号缓存 57 reg [1:0]cmos_href_d=2'd0; 58 always@(posedge cmos_pclk_i) 59 begin 60 cmos_href_d<={cmos_href_d[0],cmos_href_r}; 61 end 62 63 // Early frame discarding section 64 REG [ . 4 : 0 ] frame_cnt = 0 ; // the frame counter 65 REG OUT_EN = 0 ; // started normal operation 66 Always @ ( posedge cmos_pclk_i) 67 IF (rst_n_reg [! . 4 ]) 68 the begin 69 frame_cnt <= . 5 ' D0; 70 OUT_EN <= . 1 ' B0; 71 is End 72 the else the begin 73 is IF (vs_start)the begin 74 frame_cnt <= frame_cnt + . 1 ; 75 OUT_EN <= 0 ; 76 End 77 the else IF (frame_cnt> = CMOS_FRAME_WAITCNT) 78 the begin 79 OUT_EN <= . 1 ; 80 frame_cnt <= CMOS_FRAME_WAITCNT; // holding normal frames processed 81 End 82 End 83 // Since the output data is 24bit, 16bit data is transformed from the RGB data of two frames stitching 84 REG href_cnt = 0 ; 85 REG DATA_EN = . 1 ' B0; 86 REG [ 15 : 0 ] = RGBM 16 ' D0; // the RGB Data Middle 87 88 Always @ ( posedge cmos_pclk_i) the begin 89 IF (! rst_n_reg [ . 4 ]) the begin 90 href_cnt <= 0 ; 91 is DATA_EN <= . 1 ' B0; 92 RGBM <= 16 ' D0; 93 End 94 // after completion of the two data registration data_en a set, so that the zeroth splicing lower 8 bits active, so that the low eight 1st active (displacement) 95 the else the begin 96 href_cnt<=(cmos_href_r)?href_cnt+1'b1:href_cnt; 97 data_en<=(href_cnt==1); 98 if(href_cnt) RGBm<={RGBm[7:0],cmos_data_r}; //此处cmos_data_r lag 2 clocks，thus later all lag 2clks 99 end 100 end 101 102 assign rgb_o={RGBm[15:11],3'd0,RGBm[10:5],2'd0,RGBm[4:0],3'd0}; 103 //模块行同步输出 104 ASSIGN hs_o = OUT_EN (cmos_href_d [? 0 ]): 0 ; // for synchronization with Shucu signal, the synchronizing signal is lagging two PCLK 105 // synchronization signal output module field 106 ASSIGN vs_o = OUT_EN (cmos_vsync_r)?: 0 ; // line starting end synchronization after synchronization field, a field sync signal PCLK almost known, that the program is really nb, considered too full 107 // module data output synchronous clock signal, 12M, 108 ASSIGN de_o = OUT_EN ? DATA_EN: 0 ; 109 // output Signal clock enable 110 ASSIGN clk_ce OUT_EN = ((DATA_EN & hs_o) || hs_o!):? 0 ; // fact seems to be a line, no edge drive 111 //In the case of the init complete, d0 is the result of two pclk delay, the output synchronization signal (more precisely aligned) at the clock input of data 112 // synchronization with the 12Mhz clock data_en 113 // the each module 2 outputs a pclk rgb [23: 0] of data required heard clk_ce clock frequency synchronization, the process solves the problem of synchronization between the interface module 114 / * 115 illustrated: 116 in do == 0 when, clk_ce constant is high, no clock pulse 117 at 1 do ==, the clock is always synchronized to the clock 12M 1 18 * / 119 endmodule