[Original] NIOS taken the first step HelloNIOS

Official Release Altera NIOS been a long time, personal feeling with the code C + V would be a mainstream FPGA later used to accomplish some of the C timing insensitive, some of the high functional requirements, such as motion control; the V to match the timing of the completion of the high demand and the timing requirements of some of the underlying drivers for C to call such a structure designed to feel more reasonable and effective, but also more suitable for some large projects. But one thing is bad program portability may be a bit bad, after all editing environment using Eclipse (I'm not sure, anyway personally feel transplant up some trouble).

Well, we started our first routine, HelloNIOS . Language of software in the classic HelloWorld here became HelloNIOS, it looks very good.

Brief introduction

In fact, there are tutorials on the web about NIOS is already a lot, in this article only as a learning to use my own record. First, use NIOS, you definitely have to have the hardware to match the bar, where you start by telling me their hardware environment.

• Hardware: The development board black gold AX301
• Software: QuartusII 13.0sp1, NIOS13.0sp1

The most critical factor is that these, the development board is very common, after bought some feel less resources, but some simple development and use of NIOS and that was enough, the best use, to engage them.

Let me talk about some of the information under the reference, "NIOS fantasy drifting" and "NIOS those things", the feeling is very classic material, it can be used as entry.

Quartus Engineering established

Here and establish common hardware Quartus project is no different, I do not say here, briefly mentioned.

1. Establish Quartus Engineering, where good distribution of each part file folder (this is a personal habit, and now I have a general framework as shown below)
   
   which ipcoreis used to store official inception of the IP core, tclused to store files tcl pins, verilogused to store personal written V code.

2. Create a corresponding PLL, PLL to decide whether created here, because we have to use resources board SDRAM, which requires a 100MHz clock, but our input is 50MHz, so here need a PLL.

3. After establishing complete PLL, we have established Qsys. Qsys that previous versions of SOPC Builder, whose main is to create a virtual SOPC out. Tools - >> Qsys can be opened after opening we can see the following interface.
   

4. And then click Add NIOS, SYSID, SDRAM, EPCS, JTAG, be renamed after the connection is added. NAME renamed method is selected after press "2" or "R" can be, I usually will this all changed names several parts of the capital. This may be part of the Warning or Error occurs, the following points need some attention has been explained.
   • After a schematic diagram below shows all the components adding
     
   • After the connection according to certain rules, illustrated in Figure 17 form the connection, the lower portion still discovered the existence of the following Error.
     
     
   • Here it is necessary to set certain NIOS-core, double-click call NIOS core, make the following settings. After the setup is complete you can see Error disappeared.
     
   • Then of course there will be some downward about the address line error Warning or Error, which is the same as the address space of many components, which can be seen on the right side, similar to the screenshot below.
     
   • Then you can click System-> Assign Base Address is automatically assigned address line, where I would have a habit EPCS module address line is fixed to 0x0, the above connection can also be seen in FIG.
   • After completion of the above we should pay attention to interrupt IRQ last one, but also remember to connect them together.
   • Generation after clicking the top tab bar are generated, the page will remember check the following sections.
     
   • So far, the configuration of the end portion of Qsys.

5. Add in Quartus top of PLL and Qsys, in the form of a multi-purpose reference schematics to connect, I usually use code to connect, this part of it depends on personal preference. Use better portability of code but is not connected in schematic form intuitive.

6. Then compiled, the SOF downloaded into the FPGA development board. So far, all the work is completed in Quartus.

NIOS project established

This part of the description data according to the reference, is very simple, are abbreviated as follows.

1. Select a space for the storage project, I usually put in the catalog of Qsys
2. File -->> New -->> NIOS II Application and BSP Template
3. Sopcinfo selected files in Quartus, then name the project, all the way Next on the line
4. After the project is generated, select the left of the folder, right-NIOS II - >> Generate BSP
5. After generating, Ctrl + B compiled
6. After compilation, open the Run-Configuation, download configuration, Apply, Run
7. Finally, you can wait for the results of the commissioning box
8. Finally, put a successful outcome