Nios first experience - Hello world!

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foreword

Environment:
1. Quartus18.0
2. vscode
3. Board model: Atomic Brother Pioneer 2 (EP4CE10F17C8)
Requirements:
output Hello world through Nios!

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1. System design

1. System module block diagram

The Nios II processor is connected with ROM and RAM through the Avalon bus, where the Avalon bus is used to transmit instructions and data. In addition, the Qsys system also provides a JTAG interface for users to download and debug programs.

2. Modules involved in the system

1. Clock

The full name of the clk IP core is Clock Source, which sets the working clock frequency of our entire system here.

2、nios2_qsys

This is what we learned when we introduced Qsys before. This is the control center of the entire Qsys, which plays the main control role of allocating interrupts, managing addresses, and scheduling memory. It is equivalent to the lower part of the brain, and communicates with the outside world through Avalon.

3. On-chip storage (onchip_rom, onchip_ram)

Here we have created two on-chip memories, ROM and RAM. These two on-chip memories are implemented using the on-chip storage resources of the FPGA. In addition to storing instructions and data, they are also the running space of the program. It should be noted that the implementation of ROM does not have a dedicated ROM resource inside the FPGA. We assign an initial value to RAM and keep this value all the time to make it read-only, thereby realizing on-chip ROM (read-only memory).

4. Serial communication (jtag_uart)

The JTAG UART IP core uses the JTAG interface to implement serial communication between the host computer and the Qsys system. The JTAG UART IP core provides users with Avalon-MM interface mapping , shielding the complex JTAG interface protocol.

5、System ID（sysid_qsys）

The System ID IP core is a read-only device with an Avalon interface that generates a unique identifier (ID) for each Nios II system and writes it into the registers of the System ID core. Compilers and users can use this IP core to verify whether the compiled executable program matches the hardware environment configured into the FPGA. If the ID in the executable program is inconsistent with the ID stored in the System ID core in the FPGA, the program may fail at runtime

2. Hardware Design

Before starting the Qsys system design, we need to create a Quartus project according to our chip model, which has already been introduced here and will not be repeated here. The difference is that we need to create an additional qsys folder, and create a new hardware and software folder below to store the hardware part and software part of the qsys design respectively. Then we need to create a new ipcore folder under the prj folder to store the Quartus II project IP core.

1. Create Qsys

• Click tools->platfrom Desiger to enter the design interface:
  
• Modify the clock frequency to 100M:
  

Modify it to 100MHZ, and click finish to complete, otherwise the modification will fail.

• Add Nios II IP core:
  

• Double-click the Nios II IP core to enter the configuration interface:
  

Here we keep the default selection of "Nios II/f" kernel", and we will solve the error later, click finish.

• Added successfully:
  
• Add on-chip storage ROM IP core:
  
• Also double-click to enter the configuration interface:
  

We need to set it as ROM (read-only), set the size to 10240, which is 10KB, and the rest are default.

• In the same way, configure RAM:
  

Set the "Type" option to "RAM (Writable)", and then modify the "Total memory size" to "20480", which is 20KB. Other options keep the default settings, and finally click Finish

• Add JTAG UART IP core:
  
• Keep the default here:
  
• Add System ID IP core:
  
• Keep the default here, click finish:
  

2. Rename IP core & connection

In order to facilitate our understanding and may be used in later software programs, we try to rename it to a simple and easy-to-understand name.

• Right-click and click rename to rename:
  
• Modified name:
  
• Connection: connect the IP core:

When connecting, use the mouse to click on the corresponding node in the "Connections" column. After the connection, the hollow circle at each node will become a solid point, and the corresponding connection line will change from light gray to black.

• Connect the reset signal and clock signal to each IP core:
  
• The connection between the data master port "data_master" and the instruction master port "instruction_master":
  
• Notice:

The wiring of these two ports follows the following rules: the data master port is connected to all peripheral IP cores, and the instruction master port is only connected to the memory IP core.

• Connect the "jtag_debug_module_reset" signal:
  
• Notice:

After connecting the wires, we need to connect the interrupt signal of the jtag_uart IP core with the Nios II processor in the "IRQ" column. When a connection is interrupted, Qsys will automatically assign a priority to the interrupt.

• Double-click the Nios II IP core to set the reset address and exception address:
  

At this time, finish will report an error, let's set up the following automatic allocation first

• Set the base address allocation:
  
  After the setting is completed, the previous popularity will disappear, and then you can finish and Generate to generate the Qsys system.
• Build process:
  

3. Integrate Qsys system

• Add the .qip file generated by Qsys to the project:
  
• Configure the PLL phase-locked loop:
  Here, when we designed the Qsys system, the configuration is 100Mhz, so here we need to create a PLL IP core to achieve double frequency. Here, since the previous article has already introduced it, I will not repeat it here.
  Introduction to IP core and call of PLL_IP core

4. Top-level file instantiation:

• Open our Qsys design interface, find the qsys file in the Qsys folder and open it:
  
  
  
• Automatically generate Qsys system instantiation code:
  

But I don’t know why it can’t be generated here, so we instantiate the top-level module ourselves, put it in the rtl folder after instantiation, and add it to the project as the top-level file.

module qsys_hello_world(
 input sys_clk, //晶振时钟，50Mhz
 input sys_rst_n //按键复位，低电平有效
 );
 
 //wire define
 wire clk_100m; //Qsys 系统时钟，100Mhz
 
 //例化 pll IP 核
 pll u_pll(
 .inclk0 (sys_clk),
 .c0 (clk_100m)
 );

 //例化 Qsys 系统
 hello u_qsys(
 .clk_clk (clk_100m),
 .reset_reset_n (sys_rst_n)
 );

 endmodule

5. Compile and download operation:

• Assignment→Device:
  

• Set unused pins as high-impedance inputs:
  

• Set all the "Value" columns to "Use as regular I/O":
  

• The following is to analyze and synthesize and then assign pins for full compilation:
  
  

After the compilation is passed, the next part is the design phase of the software.

3. Software Design

• Click Nios II SBT for Eclipse under Toos:
  

• Modify the workspace to the software folder:
  

• Click ok to enter and select file→New→Nios II Application and BSP from Template to create a new Nios II project:
  

• Set up Nios II project:
  

• By default, the system helps us create a BSP (board support package), keep the default, and click finish:
  

• After clicking finish, we will find that two files have been added to the left:

• Click the point c file of c/c++, modify the output content and save:
  

• Right-click hello_world and select Build Project to compile:

Error:

Solution:
Select hello_world_bsp, right-click, and perform the following operations:

• Add a tick:
  

enable_reduced_device_drivers :
BSP provides two versions of the driver library for the peripherals of the processor: one is the version with fast execution speed but a relatively large amount of code; the other is the version with small package. By default, the version with a large amount of code is used. Here,
the enable_reduced_device_drivers: option is used to select a version with a small package size, thereby reducing the amount of code. enalbe_small_c_library: The complete ANSI C standard library is usually not suitable for embedded systems. BSP provides a series of tailored ANSI C standard libraries that occupy less resources. We can select the streamlined ANSI C standard library through the [enalbe_small_c_library] option.

• Uncheck:
  

enable_c_plus_plus: We use C language to write software programs, so there is no need to enable C++.
enable_clean_exit: When this option is selected, the system library will call exit() when the main function main() returns. When exit() is called, the I/O buffer is first cleaned up, and then _exit() is called. When this option is not selected, the system library will only call _exit(), which will save program space. For embedded system programs, generally they will not return from main(), so this option can be unchecked.

Then we click Generate first, then exit.

• Compile the whole project:
  
• Compiled successfully:
  

4. Download verification

Here we need to download two files, first download sof, and then download elf. Here we only introduce the download of elf files.

• Right-click on our project name—>run as—>Nios II Hardware:

If one step is successful, then your console will print successfully, otherwise the following pop-up window will pop up.

提示我们找不到与Nios II硬件系统的连接：

If you succeed in this step, then your console will print successfully, otherwise the following pop-up window will pop up.

The blogger has been searching for the above problem for a long time but he has not found the problem, or the solution. He discarded it for a few days, and it worked again when he opened it on the weekend. .

• After the download is complete, the console will output the corresponding information:
  

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V. Summary

To sum up, just one sentence, killing a pig with a sledgehammer, here we found that our steps are a bit complicated when implementing simple output, here, in order to facilitate our subsequent viewing steps, the blogger wrote in more detail here. In the following large projects, you will be able to appreciate the charm of Nios. Everyone should be careful when configuring, especially where the connection is made, come on! Recently, I am working on the temperature and humidity reading of DHT11 and the license plate recognition based on openvino, so stay tuned.

6. References

The above information comes from the teaching video of punctual atom or the development tutorial of Pioneer 2: official
source code of atom: https://github.com/no1jiangjiang/Nios_hello