| First, an overview of the board VPX high-performance signal processing board based on a standard 6U VPX architecture, standard FMC offers two slots, suitable for high performance electronics or radar signals against capture, playback, and related processing. By engaging the data interface in different ways FMC daughter cards, you can achieve different sampling frequencies, a different number of quantization bits, a different number of channels, the signal forms of different capture, playback, process function module. VPX high-performance signal processing board comprises a main scale the FPGA, the DSP polynuclear, large capacity DDR3 memory, the FMC slot, the IO expansion, and other on-board clock, the module principle diagram is shown below:
Second, the processing board specifications
Main FPGA Subsystem Specification
1) supports two expansion FMC daughter card, VITA57 meet standards;
2) selection of the Xilinx FPGA Virtex7 series, model-2FFG1761I XC7VX690T
. 3) 2 groups FPGA plug DDR3 SDRAM, each capacity of 4GB, bit width 64bit, 1333MHz operating speed;
4) leads to the back plate 22 pairs of LVDS P6;
. 5) group 4 × GTX lead 4 is connected to P2, each connected to the transmission rate is not less than 6Gbps, may work RapidIO, RocketIO, SATAII / III according to configure mode;
. 6), the RapidIO connected by local bus with the DSP;
7) all the FPGA provides the primary interface code library package;
DSP subsystem specifications
1) use TI DSP core 8, model TMS320C6678, the working frequency 1GHz;
2) plug 1 group DDR2 SDRAM, the capacity of 2GB, bit width 64bit, the work rate 533MHz;
. 3) provides a group of 4 × RapidIO connected to the FPGA;
. 4) via the EMIF FPGA interconnect configuration;
5) to provide a 2 × PCIe connector P2;
. 6) provided 2 Gigabit Ethernet to P4;
. 7) to provide an RS232 serial port P4;
. 8) provides a Gigabit Ethernet interface to the front panel;
9) to the front panel provides a serial RS232;
FPGA configuration subsystem specifications
1 ) selection of Xilinx's FPGA series Spartan6 Model XC6SLX100;
2) to configure the FPGA configuration control management module, module reset initialization management, network management module working clock work;
3) interconnected by LBC bus PowerPC;
4) and the external NORFLASH NandFLASH, NorFLASH capacity of 1Gb; NandFLASH capacity of 8GB;
. 5) output serial ports to the front panel 1;
6) may be implemented on the FPGA is configured by a DSO V7 FPGA for dynamically loading a program, S6 to V7 loading FPGA configuration clock is not less than 50MHz;
. 7) provides all interfaces to configure the FPGA source code and source code library package engineering. Three , daughter card equipped with: |