MMU: responsible for mapping virtual addresses to physical addresses, providing hardware mechanisms of memory access checks; the former allows multiple user process has its own separate address space, which can protect each process is using memory will not be destroyed by another process
Page Table: by one entries (descriptors), each entry stores the physical address and the virtual address corresponding to the access period or the next level page table address
TLB: For two page table needs to access memory three times, will reduce the cpu performance, through the "Find the translation cache" memory page table entries recently used, to avoid each time to find the main memory; cpu issue when a virtual address, first visit TLB, if TLB is full, the use of round-robin algorithm to find an entry, then overwrite it, and the new fill
Cache: cpu directly between main memory and a high-speed small-capacity memory, which is performed as part of the instruction or data near the instruction address transferred from the main memory storage to increase the program speed; after the Cache is enabled, data is read cpu when, if there is a copy of the Cache time data directly returned, otherwise read from main memory and stored in Cache