After the completion of the design RTL code, the need for simulation, IC design, the most common tool is the VCS (I use VCS2014). Functional simulation of RTL code, the following brief overview of the steps of a scripted way:
1. Create a folder, all the design and verification tb.v .v be copied into the folder.
2. Modify the testbench, add the following statement in the testbench, the objective is to export vcd file.
initial
begin
$ Dumpfile ( "xxx.vcd"); // filename waveform to be output can be changed
$ Dumpvars (0, u0); // u0 is instantiated top-level testbench file name, pay attention to modify the name of the actual situation
end
// time simulation of the circuit; initial # 1000 $ finish
3. Create a xxx.scr file, write vcs -R xxx.v xxx.v xxx.v + v2k + define + RTL_SAIF saved.
4. Open a terminal, enter the source xxx.scr, if not wrong, enter dve, import the file into the testbench .vcd added, add the waveform to view graphical simulation results.
These are the VCS a simple application, complex function later to learn, record.