Cognitive spi

SPI, I2C, UART serial bus protocol distinguish three kinds SPI interface and presentation, as well as the SPI interface Detailed
http://www.elecfans.com/emb/jiekou/20170508514183.html
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the SPI rate low high voltage low power consumption is low duty cycle from a plurality of devices linked to the high-speed multi-I2C communication, like mobile phones
but also to see whether the device supports from IIC ~ or the SPI
SPI can not half duplex full duplex iic
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the SCK clock signal
MOSI master out Slave
MISO master from the
SCS chip select: to select the low effective communication SPI peripheral
------------- ---------- some concepts ------------------------
1.CPOL clock polarity (c clock pol polity polar)
CPOL = 0 SCLK = active high. 1 i.e. the SCLK
the CPOL the SCLK low active. 1 = 0 = the SCLK
2.Edge edge of
a two cycle along the leading dege 0-> 1 || 1-> 0 / trailing edge 0- > ||. 1 l-> 0
3.CPHA (Clock physe) always collected data in the first few
CPHA = 0 in the first edge data acquisition
CPHA = 1 data acquired in the second edge
Here Insert Picture Description
spi registers:
notick table224: Interrupt Enable 1 = in the INTEN
intenset = 1 interrupt enable register position
intenclr = 1 Interrupt Enable Interrupt clear register 1
eNABLE = 1 1 control register write enable enable control
PSELSCK pin mapping register is used as a clock signal SCK the GPIO
PSELMOSI the MOSI pin mapped registers, as used to select the signal MASTER OUT SLAVER iN the GPIO
PSELMISO the MISO pin map registers for selecting GPIO as MASTER iN SLAVER OUT signal
RXD transmitted data receive register cluster data exists to engage two
RXD data transmit register. Before the host computer sends the data, the data should be sent by the CPU to put this
frequency SPI working clock configuration register, the higher frequency allocation, the faster the data transfer.
CONFIG: SPI controller configuration registers. For arranging data transmission rank, clock phase, clock polarity


4. The preparation of the program
functions of the present routine is implemented SPI master and slave SPI communication. We used the two - the Electronic
NRF51822EK_TM development board. Wherein as a SPI master plate, burning host program, as a SPI slave board, the burn
program. After each host transmitting a character, colorful green lamp flashes; each slave receives a character, colorful green lamp
flashes.
Procedures used pins: 1) CS-P0.13 2) MOSI-P0.14 3) MISO-P0.12 4) SCK-P0.15.
4.1 SPI controller configured
1) to select SCK, MOSI, MISO, CS signals corresponding GPIO.
2) Mode SPI mode
3) arranged high and low order
4) arranged in an SPI clock
5) arranged interrupts, interrupt polarity configuration
4.2 Example program flow
1) configure the GPIO, the lamp for lighting the RGB light green.
2) SPI controller configuration.
3) Send "Nordic" string to the SPI slave end.
4) the data transmission is completed, the development of the green light of the RGB light flashes board.
The functional verification
open project in the present embodiment, the path is: 13 speaks SPI master \ SPI master
\ examples \ peripheral \ spi \ pca10028 \ arm5_no_packs, compiled and downloaded to the development board, and then again to the development board
power , the board's RGB green light flashes to indicate SPI master is sending data. Please use another piece of board on burning
14 SPI slave talk program. Dupont line with the signal pin 2 SPI board connected together, the green light from the RGB machine will
blink.

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Origin blog.csdn.net/weixin_40654382/article/details/91040225
SPI