GD32 combat 18__ low power consumption

Why requiring low power consumption

Many people will fall into such errors, do not need no battery-powered low power consumption. At first glance, it seems quite reasonable, does not. Low power consumption is not because of the limited supply capacity to do a last resort option, but strive for long-term stable operation of the entire product is made of.

I think that every system should be considered low-power design.

Low power consumption

This article deals only with the low-power chip from the point of view, the external circuit is not discussed.

We know that the chip is essentially a bunch of gates, each gate of the switch will be accompanied by a current generating power, thus reducing power consumption is the best way to stop the operation of these gates. Therefore, to cut off its source, i.e., turning off the clock on and off. For example GD32.

1. We can slow the system clock or by peripheral or off unused clock module to achieve the purpose of reducing power consumption.
2. Domains can also control power supply, to achieve the purpose of low power consumption, for GD32 supports three power-saving mode. That is, a sleep mode, a deep sleep mode and standby mode, the following table,
3. Power consumption in each mode, the following table,

Sleep Mode

This mode corresponds to the same SLEEPING M3 mode, only the official M3 clock in this mode.

Entry method is

1. Clear SLEEPDEEP M3 System Control bit register, or the WFI into the WFE instruction.

Wake-up approach is

1. WFI instruction, any interrupt can wake up.
2. WFE instruction, any event can wake up.

Into the mechanism, in accordance with the M3 SCR (system control register) SLEEPONEXIT bit into the sleep support two mechanisms,

1. sleep-now: if SLEEPONEXIT bit is cleared, once the WFI or WFE instruction is executed, MCU immediately goes into sleep mode.
2. sleep-on-exit: If SLEEPONEXIT bit is set, when the system is separated from the lowest priority interrupt handler, MCU immediately goes into sleep mode.

Feature is the wake-up time is minimized.

code show as below,

void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY)
{
    /* Clear SLEEPDEEP bit of Cortex-M3 System Control Register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
    
    /* Select WFI or WFE to enter Sleep mode */
    if(PWR_SLEEPENTRY == PWR_SLEEPENTRY_WFI)
    {
        __WFI();
    }
    else
    {
        __WFE();
    }
}

Deep Sleep Mode

This mode corresponds to the same SLEEPDEEP M3 mode, in this mode, all clock domains 1.2V all closed, HSI, HSE, and PLL are all disabled.

Entry method is

1. The system control registers SLEEPDEEP position M3 1
2. Clear SDBM bit PWR_CTLR register
3. The WFI or WFE instruction to enter immediately

Wake-up approach is EXTI from any interruption or wake-up events can wake up.

Features and Notes,

1. Just exit deep sleep mode, the HSI selected as the system clock.
2. In order to successfully enter a deep sleep mode, the status of all pending EXTI line (in EXTI_PD register) and RTC alarm flag must be reset, otherwise, you can not enter the deep sleep mode.
3. LDO wake-up from low-power mode, it is necessary to wait for the delay.
4. Reserved data register and the SRAM.

Low Power LDO,

1. It may control the LDO in the normal mode or low-power mode PWR_CTLR LDOLP bit register.
2. LDO wake-up from low-power mode, it is necessary to wait for the delay.

void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY)
{ 
    uint32_t temp = 0;
    
    /* Select the LDO state in Deep-sleep mode */
    temp = PWR->CTLR;
    
    /* Clear SDBM and LDOLP bits, and select Deep-sleep mode */
    temp &= ~((uint32_t)(PWR_CTLR_SDBM | PWR_CTLR_LDOLP));
    
    /* Set LDOLP bit according to PWR_LDO value, and select the LDO's state */
    temp |= PWR_LDO;
    
    /* Store the new value */
    PWR->CTLR = temp;
    
    /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
    
    /* Select WFI or WFE to enter Deep-sleep mode */
    if(PWR_DEEPSLEEPENTRY == PWR_DEEPSLEEPENTRY_WFI)
    {
        __WFI();
    }
    else
    {
        __SEV();
        __WFE();
        __WFE();
    }
    /* Reset SLEEPDEEP bit of Cortex-M3 System Control Register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}

Standby mode

This pattern can be seen as an upgraded version of SLEEPDEEP mode, the 1.2V domain power failure all, LDO, HSI, HSE, PLL is also off.

Entry method is

1. The system control register M3 SLEEPDEEP position 1,
2. SDBM PWR_CTLR location register,
3. Clear WUF bit PWR_STR register
4. WFI or WFE instruction into the execution immediately.

Inspection method, the SBF can be judged by the status bit register PWR_STR MCU is in standby mode.

Wake-up method, only the following four kinds

1. NRST external reset pin
2. RTC Alarm
3. IWDG reset
4. Rising WKUP pin

feature is,

1. Lowest power, longest wake
2. SRAM and register content is lost, except for backup register
3. When the standby mode, power-on reset occurs

void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY)
{
    /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    /* Set SDBM bit, and select Standby mode */
    PWR->CTLR |= PWR_CTLR_SDBM;
        
    /* Reset Wakeup flag */
    PWR->CTLR |= PWR_CTLR_WUFR;
    
    /* Select WFI or WFE to enter Standby mode */
    if(PWR_STDBYENTRY == PWR_STDBYENTRY_WFI)
    {
        __WFI();
    }
    else
    {
        __WFE();
    }
}