1. SPM and clock request signal control process
Because the whole system is not only AP (MCU), but also subsystems such as modem and connectivity; after the CPU enters the WFI, the whole system relies on an SCP: SPM to control the sleep/wake up process, and it will pay attention to the status of each subsystem
SPM = System Power Manager , it controls the key logic of whether the system can drop to the minimum current after cpu suspend , you can understand it as a voting mechanism, when the key resources ( memory, clock) of the system are not used by anyone, It will put the system into a true deep sleep state (minimum current) as long as it detects that any resource requests have not been released, the system cannot go down to the bottom
Therefore, in the debug process of the bottom power problem, we not only check whether the cpu has suspend successfully, but also whether the state of the SPM is correct.
There is a programmable controller PCM (Programmable Command Master) in the SPM
The CPU will write the firmware of the SPM into the PCM before entering the WFI , and then the PCM will control the work of the SPM according to the logic of the firmware.
One thing that is strongly related to SPM is the clock request signal in the system, that is, the control logic of the 26M clock switch; because when the system works at the minimum current, the SPM only relies on the 32K clock to work; therefore , it is necessary to judge whether the system has reached deep sleep Status, depends on whether 26M is closed
The outline of the control logic of the 26M clock is as follows
So from the above figure, we can see that whether 26M is relevant, we only need to see if the SCLKENA signal is turned off; and the SPM output of this signal and the signal input of the subsystem will be recorded in the SPM register. This is our The basis for checking through the log
code path:
/kernel-x.x/drivers/misc/mediatek/base/power/spm_vx/
二、Deep idle
basic concept
This is a state after the CPU enters idle, that is , executed in the idle process
Simply put, Mediatek will turn off some unnecessary power domains when the CPU is idle to achieve the most power saving purpose, because when the CPU is idle, there are actually many domains in the system that do not need to run. Yes, if you don't do this, the power of the CPU will only be saved, and the purpose of power saving will not be achieved.
Mediatek's approach is that after the CPU enters the idle process, it will judge whether the current system state meets the conditions for entering a more power-saving state. First, it will check whether it can enter deep idle, because dpidle is the most power-efficient.
The conditions that the system needs to meet to enter dpidle are:
single core ( BY_CPU )
All the preset clocks that can block deep idle have been closed (BY_CLOCK)
The CPU does not need to be dispatched from the idle task within 2ms ( BY_TMR )
BY_VTG / BY_OTH的case很少（BY_OTH在个别平台跟TEE（SPI指纹模块）有关）
我们可以从波形上检查系统是否进入deep idle
下图中电流的底部就是deep idle的状态，在MP3播放的状态大约20mA；
如果没有进deep idle，这个底部会被抬高
deep idle也是由SPM来控制它的执行逻辑，跟suspend一样， CPU在进去WFI之前会把SPM的firmware写入PCM，这个firmware跟suspend是完全不一样的。
三、背景知识---SODI
SODI跟deep idle类似，是SPM的另外一种工作模式
SODI：Screen On Deep Idle
SODI的进入条件跟deep idle是类似的，区别只是要检查的clock跟deep idle不完全一样 ，SODI对display功耗的影响相对于CMD / VDO mode是不一样的
前面讲过了CMD / VDO的差别，其实就很容易理解这一点：因为CMD mode下，CPU不用送数据出去，因此MIPI clock可以不用送，这整条clock路径上的东西（PLL/clock）都可以关闭，而且memory跟VDO相比也可以做更多省电的action；所以SODI对CMD mode的省电效果会比VDO的效果更明显
是否进入SODI也可以从波形上明显地看到：
下图示SODI enable/disable的idle mode波形比较
CMD mode：SODI on(左) vs SODI off(右)
VDO mode：SODI on(左) vs SODI off(右)
*重点关注波形的形状，电流下降的数值不同平台不一样